Lead Digital Verification Engineer—ASIC/Serdes (Wavelogic)

Ciena; New York (NY); On-site; USD 147,100 - 234,900; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(k) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays and vacation

Job summary

Ciena is seeking an expert digital verification engineer for our Rochester, NY office. You will lead the verification of the Wavelogic family, collaborating with a team of digital design engineers and architects to validate cores and subsystems using mixed simulation, formal methods, and coverage-based techniques.

The role requires a bachelor’s degree in Electrical/CS and deep experience with SystemVerilog, UVM, SVA, and industry-standard simulators.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or CS.
• Expert level SystemVerilog/UVM/SVA experience.
• Experience with simulators from major vendors.
• Strong English communication skills.
• Ability to mentor and lead teams.

Responsibilities

• Validate digital subsystems using simulation, formal, and coverage methods.
• Create and optimize testbenches and verification plans.
• Estimate schedules and report progress to management.
• Collaborate with systems engineers and architects.

Skills

SystemVerilog

UVM

SVA

Simulators

Digital verification

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Tools

Jira

GIT

Python

C

C++

Job description

Ciena is seeking an expert digital verification engineer for our Rochester, NY office. You will lead the verification of the Wavelogic family, collaborating with a team of digital design engineers and architects to validate cores and subsystems using mixed simulation, formal methods, and coverage-based techniques.

The role requires a bachelor’s degree in Electrical/CS and deep experience with SystemVerilog, UVM, SVA, and industry-standard simulators.