Lead Digital RTL Design Engineer for Power Management ICs

Renesas Electronics Corporation; Austin (TX); On-site; USD 120,000 - 210,000; Full time

Job summary

Renesas Electronics is seeking a senior digital design lead to develop, debug, and verify digital designs in pre- and post-silicon environments for advanced power management ICs.

You will mentor junior engineers, craft tests in SystemVerilog, work with Cadence or Synopsys flows, and collaborate across design blocks to deliver robust, industry-leading chips.

10+ years in EE/ECE and strong communication are required, along with experience with I2C/I3C/SPI/I2S and scripting for automation.

Qualifications

• BSc or MSc in EE/ECE with 10+ years of relevant industry experience.
• Proficient in Verilog for CDC/RDC/LINT and mixed-signal debugging.
• SystemVerilog test benches and gate-level simulation experience.
• Experience with serial interfaces (I2C/I3C/SPI/I2S).
• Strong analytical and communication skills; leadership in projects.
• Experience with Cadence or Synopsys design flows.

Responsibilities

• Develop, debug, and verify digital designs in pre- and post-silicon environments.
• Write tests to verify bulk design intent as per specification.
• Learn, develop and improve scripts to facilitate design automation flows.
• Manage assigned design blocks in requirements, architecture, and implementation.
• Research and present new tools to aid design development.
• Act as technical mentor for junior engineers.
• Represent digital design as functional design lead in projects.

Skills

Verilog CDC RDC LINT

SystemVerilog test benches

Debugging mixed-signal designs

I2C/I3C/SPI/I2S interfaces

Design leadership

Communication skills

Python/Perl scripting

Cadence/Synopsys flows

Education

BSc/MSc in Electrical Engineering/Computer Engineering

Tools

Cadence tools

Synopsys tools

Job description

Renesas Electronics is seeking a senior digital design lead to develop, debug, and verify digital designs in pre- and post-silicon environments for advanced power management ICs.

You will mentor junior engineers, craft tests in SystemVerilog, work with Cadence or Synopsys flows, and collaborate across design blocks to deliver robust, industry-leading chips.

10+ years in EE/ECE and strong communication are required, along with experience with I2C/I3C/SPI/I2S and scripting for automation.