Lead Digital ATE Test Engineer for High-Speed Modems & SoCs

Socket.dev; Sunnyvale (CA); On-site; USD 183,000 - 248,000; Full time

Job summary

Amazon is seeking a Senior Modem ATE Test Engineer in Sunnyvale to lead end-to-end digital ATE test development for complex ASIC/SoC and modem devices. You will drive test definition, fault-model content, and production release, coordinating with design, DFT, and manufacturing teams to optimize testability and cost-efficiency.

You will own test programs on Advantest 93K and Teradyne UltraFLEX, develop MBIST/memory repair flows, and push for robust production limits while reducing test time.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or equivalent is required.
• 7+ years of digital ATE test development experience, preferably in high-volume manufacturing.
• Experience testing complex SoCs and modem/wireless devices in advanced nodes.
• Experience developing and debugging test programs on Advantest 93K and/or Teradyne UltraFLEX platforms.
• Familiarity with JTAG and boundary-scan, and with DFT/DFM principles.
• Experience with digital test methodologies such as scan/ATPG, MBIST, Vmin, and loopback.
• Proficiency in high-speed SERDES test at 100G+, including equalization and jitter analysis.
• Experience with wafer sort and final test ATE hardware bring-up and debugging.
• Strong written and verbal communication skills.
• Willingness to travel internationally during release-to-production phases.

Responsibilities

• Develop, debug, and release digital test programs for complex ASIC/SoC and modem devices on Advantest 93K and/or Teradyne UltraFLEX platforms.
• Build and debug scan/ATPG content for complex devices.
• Implement MBIST and memory repair flows.
• Characterize silicon performance and process variation through ring oscillator tests.
• Test and debug I/O interfaces such as I3C, SPI, and GPIO.
• Optimize high-speed SERDES/HSIO test including equalization and jitter analysis.
• Convert test patterns from the DFT team into tester formats and validate on hardware.
• Bring up and characterize new devices; define test conditions and shmoo to establish production limits.
• Lead device correlation between wafer sort and final test; resolve measurement offsets.
• Reduce test time and cost while maintaining coverage and quality for digital and DC tests.
• Design and review FT and WT hardware, including load boards and probe cards for high-speed interfaces.
• Collaborate with ASIC design and DFT teams to ensure design-for-testability in advanced nodes.
• Analyze production data to drive yield, quality, and test efficiency improvements.
• Identify readiness gaps and drive them to resolution across the product lifecycle.
• Support qualification activities such as HTOL and ESD; mentor junior engineers.

Skills

Digital ATE test development

JTAG & boundary-scan

DFT/DFM principles

100G+ SERDES testing

Test content debugging

Wafer sort & final test experience

Python scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Advantest 93K

Teradyne UltraFLEX

Job description

Amazon is seeking a Senior Modem ATE Test Engineer in Sunnyvale to lead end-to-end digital ATE test development for complex ASIC/SoC and modem devices. You will drive test definition, fault-model content, and production release, coordinating with design, DFT, and manufacturing teams to optimize testability and cost-efficiency.

You will own test programs on Advantest 93K and Teradyne UltraFLEX, develop MBIST/memory repair flows, and push for robust production limits while reducing test time.