Lead Circuit Design Engineer - Low-Power ASICs

Socket.dev; Beaverton (OR); On-site; USD 150,000 - 190,000; Full time

Job summary

Socket.dev is seeking a Circuit Design Engineering Lead in Beaverton, OR to guide a small team in a high‑impact SOC design effort. You will drive standard cell development, PPA optimization, and new circuit ideas from concept through silicon.

You will collaborate with CPU, SOC and GPU teams, work with foundries on iPDK and DRM requirements, and ensure robust, power‑efficient layouts in a rapidly evolving technology space.

Qualifications

• Bachelor's Degree + minimum of 3 years of experience.
• 3+ years of experience in Standard cells circuit development.
• Proven experience leading & mentoring a small team.
• Strong influence, excellent interpersonal skills & able to work with multi-functional teams.
• Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, Virtuoso.
• Design experience in advanced tech node device behavior with understanding of layout rules.
• Design experience in flop, complex Standard Cells design & Power Management Cells.
• Knowledge of circuit robustness analysis.
• Experience in scripting in Perl and/or TCL.

Responsibilities

• Drive development of high performance, low power optimized standard cells to improve design PPA.
• Drive development of optimal level shifters, retention designs, etc that cater to today’s Low Power Design Requirements.
• Identify next generation of new ideas to drive PPA improvements further
• Engage with CPU, SOC and GPU teams on chip level integration requirements.
• Drive Circuit QA checks & analysis, develop new methodologies based on new design requirements.
• Work with foundries on DRM compliant layout checkers and iPDK requirements.
• Plan & drive development of designs like new circuits & tech node enablement.
• Manage migration to new PDK, PDV of standard cells & releases.

Job description

Socket.dev is seeking a Circuit Design Engineering Lead in Beaverton, OR to guide a small team in a high‑impact SOC design effort. You will drive standard cell development, PPA optimization, and new circuit ideas from concept through silicon.

You will collaborate with CPU, SOC and GPU teams, work with foundries on iPDK and DRM requirements, and ensure robust, power‑efficient layouts in a rapidly evolving technology space.