Principal ATE Test Engineer

Astera Labs; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Flexible time off in the US

Parental leave

401K

Retirement and pension plans

Medical, dental, and vision plans

Job summary

Astera Labs is seeking a Principal ATE Test Engineer to lead the development and support of complex mixed-signal silicon SoC test solutions. You will drive ATE programs from design to high-volume production and collaborate with manufacturing partners to optimize tester resources and coverage.

The candidate should have strong knowledge of high-speed protocols (PCIe, Ethernet, Infiniband, DDR, NVMe, USB) and a solid EE foundation with 8+ years of release experience.

Qualifications

• Bachelor’s in Electrical Engineering required; Master’s preferred.
• 8+ years experience releasing complex SoC to high-volume manufacturing.
• Experience with ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Proficiency in C/C++ and Python; strong communication and teamwork.

Responsibilities

• Develop and oversee SoC test strategy for high-volume manufacturing.
• Interact with manufacturing partners to define and implement ATE programs.
• Own the product from design, initial samples through ramp to high volume production.
• Collaborate with design team to define test strategy and test plans.
• Lead test pattern optimization and DFx for maximum coverage and yield.

Skills

ATE programming

C/C++

Python

SerDes 16Gbps+

Test pattern optimization

DFT techniques

SCAN

MEMBIST

Oscilloscopes

Protocol analyzers

Education

Bachelor’s in Electrical Engineering

Master’s degree preferred

Tools

Teradyne ATE

Advantest 93k ATE

Load boards design

Oscilloscopes

Protocol analyzers

Job description

• We are looking for Principal ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans

The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production rampThe candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etcEntrepreneurial, open-mind behavior and can-do attitudeWorking knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etcStrong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred≥8-year experience releasing complex SoC/silicon products to high volume manufacturingStrong team player with good communication skills to work alongside a team of high caliber engineersProfessional attitude with ability to execute on multiple tasks with minimal supervisionSkilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debugProficiency in, at least, one modern programming language such as C/C++, PythonTester platform selection, design, and development of ATE hardware for wafer sort and final testProven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product qualityExpertise in production test of high speed SerDes operating at 16Gbps and higherExperience with using Teradyne or Advantest 93k ATE platformCollaboration with design team to define test strategy, create and own test planStrong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional testsFamiliar with high-speed load board design techniquesSkilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etcExperience with lab equipment including protocol analyzers and oscilloscopesHands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platformsExperience in running External loopback at wafer sortFluent in data processing using high level programming languagesFamiliarity with modern databasesBasic knowledge of RF Testing on ATE Platform