Lead ASIC Verification Architect

Asteralabs; California (MO); On-site; USD 185,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Incentives

Benefits

Job summary

Asteralabs in California is looking for a Principal Design Verification Engineer to lead the functional verification of advanced ASICs and develop robust verification methodologies. Candidates should possess 8+ years of experience in SoC verification and be proficient in SystemVerilog/UVM, C/C++, and Python.

The role involves comprehensive verification processes, working closely with RTL designers and validation teams. Competitive salary range from $185,000 to $230,000, plus potential bonuses and benefits offered.

Qualifications

• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM with hands-on verification experience.
• Strong debugging and coverage analysis skills.

Responsibilities

• Lead the functional verification of advanced ASICs, including test planning and coverage analysis.
• Collaborate with validation teams to execute test plans on emulation platforms.
• Apply verification techniques using SystemVerilog/UVM and relevant tools.

Skills

SystemVerilog/UVM

C/C++

Python

Debugging skills

Coverage analysis

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Simulators

Version control systems

Regression systems

Job description

Asteralabs in California is looking for a Principal Design Verification Engineer to lead the functional verification of advanced ASICs and develop robust verification methodologies. Candidates should possess 8+ years of experience in SoC verification and be proficient in SystemVerilog/UVM, C/C++, and Python.

The role involves comprehensive verification processes, working closely with RTL designers and validation teams. Competitive salary range from $185,000 to $230,000, plus potential bonuses and benefits offered.