Lead ASIC Design Engineer for Satellite Communications (LEO)

Amazon Inc.; San Diego (CA); On-site; USD 154,000 - 215,000; Full time

Job summary

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites, delivering low-latency broadband worldwide. Amazon is hiring an ASIC Digital Design Engineer to define and implement digital SOCs for communications via LEO satellites and gateways.

You will work on system architecture, RTL, timing/power optimization, and first‑time silicon quality, collaborating with system architects and verification teams to meet stringent performance targets.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience troubleshooting and debugging technical systems with strong analytical skills and effective communication.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.

Responsibilities

• Implement wireless system architecture in silicon from system spec to RTL and chip-level validation.
• Build high‑performance digital solutions leveraging AI-assisted techniques to optimize throughput, latency, and availability within power and cost constraints.
• Drive high quality designs for first-time silicon success and meet PPA objectives.
• Collaborate with verification using UVM/SystemC/DPI‑C for system-level test benches and test plan development.

Skills

Troubleshooting

Analytical skills

Communication

Software development

System verification

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical or Communications Engineering (preferred)

Tools

UVM

SystemC

DPI-C

Python

Perl

Job description

Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites, delivering low-latency broadband worldwide. Amazon is hiring an ASIC Digital Design Engineer to define and implement digital SOCs for communications via LEO satellites and gateways.

You will work on system architecture, RTL, timing/power optimization, and first‑time silicon quality, collaborating with system architects and verification teams to meet stringent performance targets.