Lead Analog Layout Engineer - High-Performance SoC

Meta Careers; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Meta is seeking an experienced Analog Layout Lead in Sunnyvale, CA to drive full-custom layout of high-performance analog and mixed-signal blocks for custom chips powering VR/AR wearables. You will define layout methodologies and partner with circuit design and verification teams to meet aggressive power, performance and area targets.

You will own physical verification closure, contribute to floorplanning, and mentor engineers, ensuring parasitic-aware designs and robust signal integrity across

Responsibilities

• Lead full-custom layout of complex analog and mixed-signal blocks including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon targeting VR and AR wearable platforms
• Define and enforce analog layout methodologies, design rules, and best practices across the physical design team
• Drive parasitic-aware layout strategies to meet stringent noise, matching, and signal integrity requirements for mixed-signal designs
• Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results
• Own physical verification closure including DRC, LVS, and antenna checks across advanced process nodes
• Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts
• Provide technical guidance and layout direction to other engineers on the team, reviewing layouts and driving consistency in methodology

Job description

Meta is seeking an experienced Analog Layout Lead in Sunnyvale, CA to drive full-custom layout of high-performance analog and mixed-signal blocks for custom chips powering VR/AR wearables. You will define layout methodologies and partner with circuit design and verification teams to meet aggressive power, performance and area targets.

You will own physical verification closure, contribute to floorplanning, and mentor engineers, ensuring parasitic-aware designs and robust signal integrity across