Lead AI-Driven EDA Verification Architect

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 232,000 - 368,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA seeks an experienced Principal EDA R&D Engineer to pioneer next-generation Hardware Formal Verification tools. Lead research, architecture, and development of core engines, enhanced by Agentic AI frameworks, with multi-agent AI networks to scale large builds and optimize solver strategies.

You'll apply deep algorithmic expertise in formal methods, implement high-performance C/C++ code, and work with RTL languages (SystemVerilog/VHDL/Verilog) to produce production-grade EDA solutions in a

Qualifications

• Ph.D. or Master’s in CS/EE or related quantified field.
• 15+ years of R&D in commercial or advanced academic EDA hardware verification.
• Deep knowledge of formal methods, BMC, IC3/PDR, and theorem proving.
• Expert C/C++ (Modern C++17/20) with performance focus.

Responsibilities

• Architect and advance new formal verification algorithms (Model Checking, SAT/SMT, BDDs).
• Design and deploy multi-agent AI systems that analyze RTL and partition design spaces.
• Develop intelligent orchestration where agents collaborate to bypass state-space explosion.
• Generate SystemVerilog Assertions from natural language specs and architecture intent.
• Drive features from research to production in high-performance C/C++ environments.

Skills

C++ (Modern)

Multi-agent AI

Parallel programming

Education

PhD or MSc in CS/EE

Tools

LangChain

AutoGen

CrewAI

SystemVerilog

VHDL

Verilog

Job description

NVIDIA seeks an experienced Principal EDA R&D Engineer to pioneer next-generation Hardware Formal Verification tools. Lead research, architecture, and development of core engines, enhanced by Agentic AI frameworks, with multi-agent AI networks to scale large builds and optimize solver strategies.

You'll apply deep algorithmic expertise in formal methods, implement high-performance C/C++ code, and work with RTL languages (SystemVerilog/VHDL/Verilog) to produce production-grade EDA solutions in a