FPGA Verification Engineer - Satellite Networking (Leo)

Amazon Inc.; Sunnyvale (CA); Sur place; USD 177 000 - 247 000; Plein temps

Résumé du poste

Amazon Inc. is seeking an FPGA Verification Engineer to build and maintain UVM-based verification environments for FPGA subsystems supporting Project Leo.

You will collaborate with design and systems teams to verify digital designs for networking functions using the latest simulation-based verification methods. You will develop self-checking testbenches, plan constrained-random tests, analyze coverage data, and mentor junior engineers while contributing to an innovative satellite bus FPGA

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong debugging skills.
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.

Responsabilités

• Verify FPGA solutions and develop/maintain UVM test environments for FPGA subsystems.
• Develop constrained-random, metric-driven test plans for FPGAs performing signal processing and control functions.
• Collect and analyze coverage metrics to improve test effectiveness.
• Mentor junior engineers and contribute to DV team growth.
• Create reusable Verification IP shared across the organization.
• Support upgrades to processes and methodologies.

Connaissances

Debugging skills

UVM expertise

SystemVerilog

FPGA verification

Python scripting

Verilog

Formation

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical or Communications Engineering or related field

Outils

Python

Perl

Description du poste

Amazon Inc. is seeking an FPGA Verification Engineer to build and maintain UVM-based verification environments for FPGA subsystems supporting Project Leo.

You will collaborate with design and systems teams to verify digital designs for networking functions using the latest simulation-based verification methods. You will develop self-checking testbenches, plan constrained-random tests, analyze coverage data, and mentor junior engineers while contributing to an innovative satellite bus FPGA