IP Verification Engineer

Ericsson GmbH; Austin (TX); On-site; USD 110,000 - 150,000; Full time

Job summary

Ericsson GmbH in Austin, TX is seeking a Senior Design Verification Engineer to lead verification efforts for ASICs in 5G infrastructure. The role involves building transaction-level models, designing UVM testbenches, and driving hardware emulation.

Candidates should have extensive RTL verification experience and strong SystemVerilog/UVM skills. Join a dynamic team that encourages innovation and collaboration in an on-site/hybrid environment.

Qualifications

• Several years of hands-on RTL verification experience at block/top level.
• Strong SystemVerilog/UVM skills for architecting testbenches.
• Proficiency in TCL, Python, or equivalent scripting.

Responsibilities

• Build transaction-level models that provide architectural confidence.
• Own the sign-off for block- and top-level verification.
• Design and build UVM environments from scratch.

Skills

RTL verification experience

SystemVerilog/UVM skills

TCL/Python/Perl scripting

Communication skills

Education

B.S. or M.S. in Electrical Engineering or Computer Engineering

Tools

Linux

Git

Job description

Senior Design Verification Engineer — ASIC IP

Silicon Verification | 5G Infrastructure | Austin, TX (On‑site, Hybrid)

Ericsson's ASICs are the backbone of next‑generation 5G networks. Join our team to lead the verification of critical silicon on the world’s largest network infrastructure.

What You’ll Own

• TLM Modeling – building transaction‑level models that give the team early architectural confidence.
• Block‑ and Top‑Level Verification – owning sign‑off at both levels of the hierarchy.
• Testbench Architecture – designing and building UVM environments from a clean slate.
• HW Emulation & Acceleration – pushing verification beyond simulation into hardware‑speed environments.
• SW‑Driven Verification – bridging the hardware/software boundary where the hardest bugs hide.
• Team Leadership – mentoring engineers, influencing methodology, and shaping how the team grows.

Required Qualifications

• Several years of hands‑on, in‑industry RTL verification experience at block and/or top level.
• Strong SystemVerilog/UVM skills – not only use but architect testbenches.
• Experience building testbenches from the ground up.
• Familiarity with SerDes, PCIe, ARM subsystems, DSP/accelerators, or Ethernet.
• Proficiency in TCL, Python, Perl, or equivalent scripting.
• Strong communication skills that match your technical depth.
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent.

Preferred Skills

• Test plan ownership and design of randomized/ directed test cases.
• Embedded software fluency – C/assembly design and testing.
• Deep architecture intuition – understanding of embedded CPUs, memory, caches, coherency protocols (ARM‑based experience a plus).
• Protocol expertise – AMBA interfaces (APB, AXI, ACE‑Lite, CHI).
• Comfort with Linux, Git, LSF, and verification toolchains.
• Leadership instinct – experience leading small teams.
• Object‑oriented coding that is reusable.

Equal Opportunity Statement

Ericsson is an Equal Opportunity employer. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. If you need assistance or accommodation due to a disability, please contact Ericsson at [e-mail].