ASIC Verification Engineer – Hybrid 5G IP & Testbench

Ericsson; Austin (TX); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

401(k) matching

Stock Purchase Plan

Health benefits

Paid time off

Job summary

Ericsson Austin is hiring an ASIC Design Verification Engineer to join the ASIC IP team. You will own verification across the full stack, building robust UVM environments and testbenches for production silicon powering live 5G networks.

You will work in a hybrid environment in Austin, TX, collaborating with hardware and software teams to verify IP blocks, SerDes/PCIe/ARM subsystems, and AMBA interfaces. A strong background in SystemVerilog, UVM, and RTL debugging is required.

Qualifications

• Proficient in SystemVerilog and UVM.
• Experience building testbenches from scratch.
• Ability to debug at block/top level using waveform analysis.
• Familiar with HP/embedded CPU interfaces and RTL verification.

Responsibilities

• Lead verification across full stack in ASIC/IP projects.
• Design and implement UVM environments and testbenches.
• Drive coverage closure from block to chip-level.
• Bridge hardware verification with embedded software for real-world behavior.

Skills

SystemVerilog

UVM

RTL verification

Testbench architecture

Scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

AMBA APB/AXI/ACE-Lite/CHI

Job description

Ericsson Austin is hiring an ASIC Design Verification Engineer to join the ASIC IP team. You will own verification across the full stack, building robust UVM environments and testbenches for production silicon powering live 5G networks.

You will work in a hybrid environment in Austin, TX, collaborating with hardware and software teams to verify IP blocks, SerDes/PCIe/ARM subsystems, and AMBA interfaces. A strong background in SystemVerilog, UVM, and RTL debugging is required.