ASIC Design Verification Engineer

Ericsson GmbH; Austin (TX); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Health benefits

Company-sponsored 401(k) contributions

Paid time off

Maternity and parental leave at 100% pay

Educational assistance

Job summary

Ericsson GmbH in Austin, Texas is looking for an ASIC Design Verification Engineer to join their team. This role involves building transaction-level models and performing block-level ASIC verification. Candidates should possess several years of hands-on verification experience and a proven track record with SystemVerilog and UVM.

In addition to a competitive salary, Ericsson offers multiple medical and dental plans, a 401(k) plan with company contributions, generous paid time off, and support for maternity/parental leave.

Qualifications

• Several years of hands-on RTL verification experience in IP, ASIC, or SoC.
• Deep experience with SystemVerilog and UVM.
• Proven ability to architect and build testbenches from the ground up.
• Block- and/or top-level RTL debug experience.
• Familiar with SerDes, PCIe, ARM Subsystems, DSPs/Accelerators or Ethernet.
• Scripting proficiency in TCL, Python, Perl or equivalent.

Responsibilities

• Build transaction-level models that drive architectural verification.
• Perform ASIC/IP verification, owning coverage closure from block to chip.
• Design and build UVM testbenches from scratch.
• Bridge the gap between hardware and embedded software.
• Maintain a fast-moving verification environment.

Skills

SystemVerilog

UVM

RTL verification

TCL scripting

Python

Perl

Clear communication

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Job description

ASIC Design Verification Engineer – Austin, Texas

Hybrid work schedule. This is not a remote work opportunity.

Responsibilities

• Build transaction‑level models (TLM) that drive early architectural verification.
• Perform block‑ and top‑level ASIC/IP verification, owning coverage closure from block to chip.
• Design and build UVM testbenches from scratch, not inheriting existing shortcuts.
• Bridge the gap between hardware and embedded software to verify real‑world behavior using SW‑driven verification.
• Maintain a fast‑moving environment where new designs are built, broken, and bugs that matter are found.

Qualifications

• Several years of hands‑on, industry RTL verification experience in IP, ASIC, or SoC.
• Deep, practical experience with SystemVerilog and UVM.
• Proven ability to architect and build testbenches from the ground up.
• Block‑ and/or top‑level RTL debug experience, capable of locating hidden waveforms.
• IP familiarity with at least one of: SerDes, PCIe, ARM Subsystems, DSPs/Accelerators, or Ethernet.
• Scripting proficiency in TCL, Python, Perl, or equivalent.
• Clear, confident communicator who can explain findings and their impact.

Preferred Experience

• Developing full test plans and directed/randomized test cases from scratch.
• Object‑oriented programming skills reflected in verification code.
• Embedded software design and test experience.
• Fluency in Linux, GIT, and LSF development environments.
• Hands‑on experience with AMBA APB, AXI, ACE‑Lite, or CHI interfaces.
• Familiarity with computer architecture: CPU pipelines, memory hierarchies, cache coherency protocols.
• Early leadership instincts and a desire to grow them.

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent hands‑on experience.

Equal Opportunity Employer

Ericsson is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Compensation & Benefits

The salary range for this position is dependent on various factors including location and the candidate’s qualifications, experience, and training. The compensation package includes a competitive base salary, a short‑term variable compensation plan, and an annual bonus opportunity based on performance. Health benefits include multiple medical and dental plan options, with company credits covering the cost for employees and eligible dependents. The Ericsson U.S. 401(k) plan offers an automatic 3% company contribution and matching contributions up to 4% of eligible pay. Additional benefits comprise basic life and disability coverage, a Stock Purchase Plan, financial wellness programs, educational assistance, matching gifts, and recognition initiatives. Paid time off includes a minimum of 15 vacation days, up to 3 personal days per year, 11 holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Maternity and parental leave are provided at 100% pay for up to 16 and 6 weeks respectively.