IP Design Verification Engineer

Intel Corporation; Hillsboro (OR); Hybrid; USD 106,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel Corporation in Hillsboro, Oregon, seeks an experienced verification engineer to develop scalable UVM testbenches and drive pre-silicon validation strategies for next-generation digital designs.

You will build RTL components, define verification plans, and collaborate with IP teams to ensure robust SoC validation while advancing power and coverage methodologies across multiple projects.

Qualifications

• Experience with pre-silicon logic validation using SystemVerilog and UVM.
• Experience in Digital design using Verilog and SystemVerilog.
• Experience with pre-silicon validation closure across multiple projects.
• Hands-on experience with UVM testbench design, with a focus on reusability and scalability.
• Experience with SystemVerilog Assertions (SVA) for coverage closure.
• Scripting proficiency in Python, Perl, or TCL for design and verification automation.

Responsibilities

• Design & Develop Verification Environments – Build and maintain scalable, reusable UVM-based testbenches and test cases for complex CMOS designs at block, subsystem, and SoC levels.
• Define Verification Strategy – Own and drive comprehensive verification plans for complex digital systems across multiple projects.
• RTL Development & Integration – Develop RTL designs and integrate logic components into SoC architectures, collaborating with IP providers to validate IPs at system level.
• Power Methodology – Develop and implement power verification methodologies for complex mixed-signal IPs.
• Assertion-Based Verification – Create and apply SystemVerilog Assertions (SVA) to strengthen coverage closure and improve verification quality.
• Debug & Root Cause Analysis – Identify, debug, and resolve pre-silicon failures and drive issues to closure.
• Cross-Team Collaboration – Partner with architecture, physical design, and post-silicon teams to continuously improve verification strategies.
• Continuous Improvement – Incorporate post-silicon learnings into enhanced pre-silicon verification methodologies.
• Documentation & Reviews – Maintain detailed test plans and lead technical reviews with design and architecture teams.

Skills

UVM

SystemVerilog

Verilog

Python

Debugging

Collaboration

Education

Master's degree in Electrical/Computer Engineering

Bachelor's degree in Electrical/Computer Engineering

Tools

Verilog/SystemVerilog

UVM

SVA

Python

UPF

Job description

Job Details:Job Description:About the RoleJoin our Logic Design and Validation group within the Design Technology Platforms department, where you'll play a key role in shaping the future of semiconductor technology. You'll be part of a dynamic team responsible for developing RTL models and pre-silicon validation tests for test chips on next-generation silicon manufacturing processes. This is an opportunity to work at the cutting edge of chip design, collaborating across multidisciplinary teams to deliver robust, high-quality silicon.What You'll DoWhat You'll DoDesign & Develop Verification Environments – Build and maintain scalable, reusable UVM-based testbenches and test cases for complex mixed-signal CMOS designs at the block, subsystem, and SoC levels.Define Verification Strategy – Own and drive comprehensive verification plans for complex digital systems, ensuring thorough coverage closure across multiple projects.RTL Development & Integration – Develop RTL designs and integrate logic components into SoC architectures, collaborating with IP providers to validate IPs at the system level.Power Methodology – Develop and implement power verification methodologies for complex mixed-signal IPs using industry-standard frameworks.Assertion-Based Verification – Create and apply SystemVerilog Assertions (SVA) to strengthen coverage closure and improve overall verification quality.Debug & Root Cause Analysis – Identify, debug, and resolve pre-silicon failures, implementing corrective measures and driving issues to closure.Cross-Team Collaboration – Partner with architecture, physical design, and post-silicon teams to continuously improve verification strategies for complex architectural features.Continuous Improvement – Incorporate post-silicon learnings and feedback into enhanced pre-silicon verification methodologies.Documentation & Reviews – Maintain detailed test plans and lead technical reviews with design and architecture teams.Behavioral TraitsSelf-motivated with a strong sense of urgency and commitment to delivering results.Excellent communication and interpersonal skills with the ability to work effectively across teams.Strong analytical and troubleshooting skills with a structured approach to problem-solving.Clear and concise documentation and presentation abilities.Qualifications:The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsOption A: Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience.Option B: Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 3+ years of relevant experience.Experience with Pre-silicon logic validation using SystemVerilog and UVM.Experience in Digital design using Verilog and/or SystemVerilog.Experience with pre-silicon validation closure across multiple projects.Hands-on experience with UVM testbench design, with a focus on reusability and scalability.Experience with end-to-end validation strategies for complex digital systems.Experience with SystemVerilog Assertions (SVA) for coverage closure.Experience with coverage-driven verification methodologies.Scripting proficiency in Python, Perl, or TCL for design and verification automation.Preferred QualificationsExperience in Mixed-Signal IP verification (e.g., PLL, DDR, SerDes).Experience with Unified Power Format (UPF) specification and power-aware verification.Experience with synthesizable Verilog/SystemVerilog and industry-standard simulation tools.Experience with timing and power convergence tools and methodologies.Experience with AI/ML techniques and their application in verification automation and efficiency.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location:US, Oregon, HillsboroAdditional Locations:US, California, FolsomPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.