IC Packaging Design Engineer

Tessolve; Chandler (AZ); Vor Ort; USD 110.000 - 190.000; Vollzeit

Benefits dieser Stelle

Engagement with leading semiconductor/

Cutting-edge packaging projects

Flexible location Chandler or Hillsbor

Zusammenfassung

Tessolve Semiconductors is hiring IC Packaging Design Engineers for Chandler, AZ (primary) or Hillsboro, OR (secondary). Senior candidates with 10+ years are preferred; mid-level (4–6+ MS / 6+ BS) are also considered.

You’ll design IC packages, drive substrate layout, and ensure reliability, manufacturability, and SI/PI-aware implementations. Join a leading semiconductor engineering firm and work on cutting-edge packaging projects with flexible location options in Chandler, AZ or Hillsboro, OR.

Qualifikationen

• Requires 10+ years for senior or 4–6+ years MS / 6+ years BS for mid-level candidates.
• Experience in IC packaging design and substrate layout.
• Proven ability to implement SI/PI-aware designs and ensure DFM/DFY/DFR compliance.

Aufgaben

• Perform physical design and layout of IC packages
• Execute substrate design and layout
• Design for performance, manufacturability, yield, and reliability (DFM/DFY/DFR)
• Ensure design rule compliance across all deliverables
• Use Siemens Xpedition or Cadence APD for design execution

Kenntnisse

IC packaging design

Siemens Xpedition

Cadence Allegro/APD

DFM/DFY/DFR

Substrate design

Ausbildung

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Siemens Xpedition

Cadence Allegro/APD

Jobbeschreibung

Tessolve is hiring 4 IC Packaging Design Engineers based in Chandler, AZ (primary) or Hillsboro, OR (secondary). We're looking for senior-level talent (10+ years) primarily, with mid-level (4–6+ years MS / 6+ years BS) candidates also considered.

About the Role

As an IC Packaging Design Engineer, you'll work on physical design and layout of IC packages, driving substrate design and SI/PI-aware implementation for high-performance semiconductor products. You'll collaborate closely with cross-functional teams to ensure designs meet performance, manufacturability, yield, and reliability targets.

What You'll Do

• Perform physical design and layout of IC packages
• Execute substrate design and layout
• Design for performance, manufacturability, yield, and reliability (DFM/DFY/DFR)
• Ensure design rule compliance across all deliverables
• Use Siemens (Mentor) Xpedition (XPD) or Cadence Allegro/Advanced Package Designer (APD/SiP) for design execution

What You Bring

• Bachelor's or Master's degree in Electrical/Electronics Engineering
• Mid-level: 4–6+ years (MS) or 6+ years (BS) in IC packaging / package design
• Strong hands-on experience in Siemens Xpedition (XPD) or Cadence Allegro/APD (SiP)
• Proven experience in substrate design, SI/PI-aware implementation, and design rule compliance

What We Offer

• Engagement with a leading semiconductor engineering firm
• Opportunity to work on cutting-edge IC packaging projects
• Flexible location options: Chandler, AZ or Hillsboro, OR

About us:

Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.