Hybrid Senior ASIC Verification Engineer – Networking

Hewlett Packard Enterprise; Durham (AR); Hybrid; USD 135,000 - 311,000; Full time

Job summary

Hewlett Packard Enterprise in Durham, NC is seeking a Senior ASIC Verification Engineer for a hybrid role, requiring in-office presence two days per week. You will lead block- or subsystem-level verification, develop UVM environments, and drive coverage to closure on high-speed networking ASICs.

Candidates should have 7+ years in ASIC/SoC verification, SystemVerilog and UVM expertise, and experience with Cadence Xcelium, Synopsys VCS or Mentor Questa.

Qualifications

• 7+ years in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools and waveform debugging (Cadence Xcelium, Synopsys VCS, Mentor Questa).

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

Test planning

Debugging

Coverage analysis

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise in Durham, NC is seeking a Senior ASIC Verification Engineer for a hybrid role, requiring in-office presence two days per week. You will lead block- or subsystem-level verification, develop UVM environments, and drive coverage to closure on high-speed networking ASICs.

Candidates should have 7+ years in ASIC/SoC verification, SystemVerilog and UVM expertise, and experience with Cadence Xcelium, Synopsys VCS or Mentor Questa.