Hybrid Security IP Verification Engineer

Arm Limited; Austin (TX); Hybrid; USD 162,000 - 219,000; Full time

Job summary

Arm Limited is seeking creative and enthusiastic Design Verification Engineers for the Security IP Team in Austin, TX. You will verify Security IP for pioneering SoC designs, contributing to test plans, testbenches, and verification strategies in areas such as cryptography, key management, and hardware root of trust.

The role involves developing UVM and SystemVerilog/Verilog testbenches, debugging failures, mentoring teammates, and collaborating with design and project teams.

Qualifications

• Bachelors or Masters in Computer Science or Electrical/Computer Engineering with 5+ years in design or verification of sophisticated IP/SoCs.
• Security hardware, embedded processor systems, cryptography, secure boot, and key management experience.
• Experience with complex digital IP architecture including multi-clock domains, AXI/AHB, multi-power domains, and reset architectures.
• Proficiency with Perl, Python, Tcl or similar scripting languages.
• Experience verifying IP/SoC projects with firmware/hardware co-verification or formal verification.

Responsibilities

• Craft test plans and develop UVM, SystemVerilog/Verilog, and C testbenches and tests.
• Debug test failures and issues; collaborate with design teams for sign-off and coverage.
• Mentor team members and work with Project Management on initiatives and schedules.

Skills

Verilog HDL

SystemVerilog UVM

C

Formal verification

Hardware/Firmware co-verification

Embedded systems

Security IP verification

Key management

ARM architectures

AXI/AMBA protocols

Education

Bachelor's or Master’s degree in Computer Science or Electrical/Computer Engineering

Job description

Arm Limited is seeking creative and enthusiastic Design Verification Engineers for the Security IP Team in Austin, TX. You will verify Security IP for pioneering SoC designs, contributing to test plans, testbenches, and verification strategies in areas such as cryptography, key management, and hardware root of trust.

The role involves developing UVM and SystemVerilog/Verilog testbenches, debugging failures, mentoring teammates, and collaborating with design and project teams.