Hybrid CPU Core Physical Design Engineer

Intel; Folsom (CA); Hybrid; USD 106,000 - 200,000; Full time

Benefits offered by this job

Hybrid work model

Stock bonuses

Health benefits

Job summary

Intel in California's Folsom is seeking a CPU Physical Design Engineer to advance next‑gen CPUs powering AI and analytics. You will handle implementation from RTL to GDS, and work with cross‑functional teams across logic, circuit, and design automation groups.

The role requires 1–2 years of VLSI design and STA experience, plus a strong foundation in physical design concepts, clocking, and power integrity. Intel offers a hybrid work model, competitive compensation, and comprehensive benefits.

Qualifications

• Bachelor's or master's degree with 1–2 years of relevant design experience
• Experience in VLSI circuit design, static timing analysis, and low power design
• Familiarity with CPU physical design concepts and cross-functional collaboration

Responsibilities

• Performs physical design implementation from RTL to GDS to create a design database for manufacturing
• Conducts verification and signoff including formal equivalence verification, STA, and DRC/LVS checks
• Analyzes results and recommends improvements to CPU microarchitectures with cross‑functional teams
• posseses CPU‑specific expertise in physical design aspects including clock design, timing closure, and power/area optimization
• Works with industry EDA vendors to enhance tool capabilities for high‑speed, low‑power, synthesizable CPU

Skills

VLSI design

Static timing analysis

Low power design

Physical design flow

Scripting (Python/Tcl/Perl)

Education

Bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree

Master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree

Tools

EDA tools

Job description

Intel in California's Folsom is seeking a CPU Physical Design Engineer to advance next‑gen CPUs powering AI and analytics. You will handle implementation from RTL to GDS, and work with cross‑functional teams across logic, circuit, and design automation groups.

The role requires 1–2 years of VLSI design and STA experience, plus a strong foundation in physical design concepts, clocking, and power integrity. Intel offers a hybrid work model, competitive compensation, and comprehensive benefits.