HSIO Validation Lead — Silicon Co-Design (Hybrid, Equity)

NVIDIA; United States; Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's Silicon Co-Design Group seeks an experienced engineer to own post-silicon bring-up, characterization, and validation of high-speed interfaces across GPUs, CPUs, and SoCs. You will drive root-cause analyses across protocol behavior, signal integrity, and firmware interactions, delivering fixes to production readiness.

You will define validation strategies, build AI-assisted debugging pipelines, and ensure interoperability across a wide ecosystem of devices.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience in the lab.
• 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies.
• Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and high-speed board and system interactions.
• Hands-on lab depth: oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, and silicon debug tools.
• The ability to debug across the full stack, hardware, firmware, drivers, and platform design, without losing the thread.
• Enough statistical proficiency to recognize the moments a marginal distribution is telling you something and enough develop intuition to know where to look next!

Responsibilities

• Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness.
• Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation.
• Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria for each program. Your strategy is what stands between a silicon risk and a customer escape.
• Own and build AI agents that operate under your direction. These include automated debug triage, intelligent data pipelines, and analysis flows. They reduce cycle time and identify issues before production. Know where AI accelerates real work and where it introduces risk.
• Ensure robust interoperability across the full ecosystem: retimers, switches, accelerators, CPUs, GPUs, and sophisticated multi-device system topologies.
• Sit at the decision table. Your analysis drives alignment across architecture, logic design, circuit design, firmware, drivers, ATE, DGX, and product teams. Your data is what settles calls.
• Translate what you learn on real silicon into methodology and coverage improvements that make future products harder to escape.

Skills

Deep protocol expertise

HSIO bring-up

High-speed interfaces

Signal integrity

Hardware debugging

System-level thinking

Statistical analysis

Lab depth

Education

BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering

Tools

Oscilloscopes

BERTs

Logic analyzers

Protocol analyzers

Exercisers

Job description

NVIDIA's Silicon Co-Design Group seeks an experienced engineer to own post-silicon bring-up, characterization, and validation of high-speed interfaces across GPUs, CPUs, and SoCs. You will drive root-cause analyses across protocol behavior, signal integrity, and firmware interactions, delivering fixes to production readiness.

You will define validation strategies, build AI-assisted debugging pipelines, and ensure interoperability across a wide ecosystem of devices.