HSIO Validation Lead - High-Speed Interface Architect

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 168,000 - 311,000; Full time

Job summary

NVIDIA Corporation is seeking an experienced engineer to lead post-silicon bring-up, validation, and debugging of HSIO interfaces across GPUs, CPUs, and SoCs from first power-on to production readiness.

You will drive root-cause analysis across protocol behavior, signal integrity, firmware, and driver interactions, define validation strategies, and own fixes through to confirmation. Build AI-enabled debug flows to accelerate problem isolation and improve platform margins.

Qualifications

• BS or MS in Electrical/Computer/Systems Eng or equivalent lab experience.
• 8+ years in silicon validation or HSIO bring-up on real hardware.
• Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, or USB.
• Strong signal integrity and board/system interaction knowledge.

Responsibilities

• Own post-silicon bring-up, characterization, validation, and debug of HSIO interfaces.
• Define validation strategy and set test coverage, margining, and stress criteria for each program.
• Drive root-cause analysis across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities.
• Own and build AI-driven debug flows, data pipelines, and analysis to reduce cycle time.
• Ensure robust interoperability across retimers, switches, accelerators, CPUs, GPUs, and multi-device system topologies.

Skills

HSIO bring-up

PCIe expertise

NVLink expertise

CXL expertise

High-speed interfaces

Signal integrity

Debug across stack

Statistical analysis

Education

BS/MS in EE or CE

Tools

Oscilloscopes

Logic analyzers

BERTs

Protocol analyzers

Exercisers

Job description

NVIDIA Corporation is seeking an experienced engineer to lead post-silicon bring-up, validation, and debugging of HSIO interfaces across GPUs, CPUs, and SoCs from first power-on to production readiness.

You will drive root-cause analysis across protocol behavior, signal integrity, firmware, and driver interactions, define validation strategies, and own fixes through to confirmation. Build AI-enabled debug flows to accelerate problem isolation and improve platform margins.