High-Speed SerDes Design Co-op (Analog/Mixed-Signal)

AMD; Santa Clara (CA); Hybrid; USD 47,000 - 69,000; Full time

Job summary

AMD is seeking a highly motivated Analog/Mixed-Signal Design Co-op to join our world-class team in Santa Clara. You will contribute to high-speed communication and optical interconnect technologies while gaining hands-on experience with advanced analog and mixed-signal circuit design.

You will define architectures, run simulations, and model RF passive components, DACs/ADCs, PLLs, and clock networks in FinFET processes.

Qualifications

• PhD student in Electrical Engineering or a closely related field.
• Experience designing and simulating analog/mixed-signal circuits (ADCs, DACs, CTLEs, PLLs).
• Strong understanding of high-speed SerDes architectures.

Responsibilities

• Define architectures optimized for high-speed electrical and optical links.
• Perform link-level simulations with MATLAB and SPICE to validate proposed architectures.
• Model on-die RF passive components, including inductors, capacitors, and optical structures.
• Assist in the design and implementation of DACs, SAR-ADCs, sample-and-hold circuits, analog front ends, PLLs, reference generation circuits, and clock distribution networks in advanced FinFET technologies.
• Gain exposure to the design of high-speed ADC-based receivers, DAC-based transmitters, and silicon-photonics transceivers.

Skills

Analog/mixed-signal design

SerDes architectures

Circuit simulations (MATLAB/SPICE)

CMOS design (FinFET nodes)

DAC/ADC/PLL design blocks

Education

PhD student in Electrical Engineering

Tools

MATLAB

SPICE

CAD tools

FinFET design knowledge

Job description

AMD is seeking a highly motivated Analog/Mixed-Signal Design Co-op to join our world-class team in Santa Clara. You will contribute to high-speed communication and optical interconnect technologies while gaining hands-on experience with advanced analog and mixed-signal circuit design.

You will define architectures, run simulations, and model RF passive components, DACs/ADCs, PLLs, and clock networks in FinFET processes.