High Speed Interface Protocols, Principal AE

Cadence Design Systems; San Jose (CA); On-site; USD 123,200 - 228,800; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Paid vacation and holidays

Medical, dental, and vision options

Job summary

Cadence Design Systems in San Jose, CA, is seeking a Principal Applications Engineer to architect interface solutions using Cadence Serdes IP and drive customer engagements.

You will lead technical discussions, demonstrate IP performance at events, collaborate with sales, marketing, and R&D, and contribute to internal processes to grow the Serdes IP business.

This role combines technical growth and business skills, with occasional travel to customer sites.

Qualifications

• BS or MS with extensive experience in high-speed IP and interfaces.
• Knowledge of PCIe, CXL, UCIe, Ethernet, USB, MIPI, 224G, 112G.
• Strong leadership and pre-sales account management skills.
• Excellent verbal and written communication.

Responsibilities

• Technical presales and configuration of High-Speed Interface IP, including PCIe, CXL and Ethernet PHY and Controllers.
• Present Cadence’s IP portfolio and capabilities to prospective customers.
• Serve as a product expert in digital controller and PHY IPs and protocols.
• Work closely with IP Sales staff, marketing, and R&D teams to win opportunities.
• Demonstrate IP performance at industry events and to prospective customers.
• Provide quick-turn product-specific technical support to customers, field teams, architects and designers.
• Write application notes and articles for internal and/or external publication.
• Travel to customer sites may be required occasionally.

Skills

PCIe/CXL/Ethernet proficiency

Pre-sales leadership

Customer-facing communication

Education

BS in EE/CE or related field

MS in EE/CE or related

Tools

AXI/PIPE interface knowledge

PHY verification

Job description

Cadence is a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable customers to create revolutionary products and experiences.

The Cadence IP team develops industry‑leading IPs that enable customers in a variety of markets—from the endpoint to the edge to the cloud—powering data centers, automobiles, cloud, and wireless systems.

We are growing our Serdes Applications team and are looking for smart, energetic, collaborative, and creative people to help us lead the industry with our IP products.

As a Principal Applications Engineer, you will use your knowledge of different high‑speed interface standards such as PCIe, CXL, Ethernet, and USB to architect interface solutions for customers using Cadence Serdes IP and showcase the performance of the IP. You will also define internal processes and lead initiatives to improve team productivity and grow the IP business. This is a customer‑facing role that offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions to them using our Serdes IP portfolio.

Responsibilities

• Technical presales and configuration of High‑Speed Interface IP, including PCIe, CXL and Ethernet PHY and Controllers
• Present Cadence’s IP portfolio and capabilities to prospective customers
• Serve as a product expert in digital controller and PHY IPs and protocols
• Work closely with IP Sales staff, marketing, and R&D teams to win opportunities
• Demonstrate IP performance at industry events and to prospective customers
• Provide quick‑turn product‑specific technical support to customers, field teams, architects and designers
• Write application notes and articles for internal and/or external publication
• Travel to customer sites may be required occasionally

Qualifications

• BS in EE, CE or related equivalent with 15+ years of relevant work experience, or MS in EE, CE or equivalent with 10+ years of relevant work experience
• Knowledge of one or more high‑speed interface protocols – PCIe, CXL, UCIe, Ethernet, USB, MIPI, 224G, 112G
• Strong knowledge of PHY and/or controllers for one or more high‑speed interface protocols
• Individual leadership and initiative to manage pre‑sales accounts
• Excellent presentation skills and verbal/written communication skills is a must

Nice to Have

• Lab validation and demo setup skills
• Experience on high‑speed interface controller and/or PHY verification
• Knowledge of AXI and PIPE interface protocols
• Working knowledge of high‑speed interface PHY

Salary & Benefits

The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Benefits

• Paid vacation and paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• A variety of medical, dental, and vision plan options
• Additional benefits programs that please group size and workload

Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.