Head of Packaging (CPO)

SBT; Austin (TX); On-site; USD 180,000 - 280,000; Full time

Job summary

SBT is seeking a Head of Packaging in Austin, TX to lead a team of engineers and scientists developing advanced packaging for multi-chip packages and high-speed silicon photonics chips.

The role involves collaborating with cross-functional teams to reach stringent performance and reliability goals, and to transition designs from concept to high-volume production.

Qualifications

• Advanced degree required in EE/ME/Applied Physics.
• Proven experience in advanced packaging design and development.
• Experience with flip-chip, wafer-level packaging and 3D integration.

Responsibilities

• Lead and mentor a team of engineers and scientists.
• Collaborate to design and develop packaging solutions meeting performance and reliability.
• Develop and optimize packaging processes from design to production.
• Co-package optical components with silicon photonic ICs.
• Create test plans and validate package performance.
• Document designs and analyze test data for improvements.

Skills

Technical leadership

Mentoring

Cross-functional collaboration

Systems engineering

Education

Master's or Ph.D. in Electrical Engineering, Mechanical Engineering, or Applied Physics

Tools

Flip-chip packaging

Wafer-level packaging

3D integration

Job description

Overview

SBT's client has developed a groundbreaking technology platform that integrates the properties of advanced materials with the capabilities of silicon photonics, aimed at driving transformative leaps forward in the efficiency of AI workloads. This startup is attempting to solve some of the most difficult challenges facing the industry related to mathematics, engineering, and physics. The Head of Packaging will be instrumental in shaping the company’s future and pushing the boundaries of optical technology and AI hardware.

Responsibilities

• Lead and mentor a high-performing team of engineers and scientists in the development of advanced packaging solutions for multi-chip packages and high-speed silicon photonics chips.
• Collaborate with cross-functional teams to design and develop innovative packaging solutions that meet stringent performance and reliability requirements.
• Develop and optimize packaging processes, including die bonding, wire bonding, flip-chip bonding, and encapsulation, to ensure seamless transition from design to production.
• Work closely with silicon photonics and electrical engineers to co-package optical components with silicon photonic integrated circuits, ensuring reliable performance and long-term stability.
• Design and develop comprehensive test plans to evaluate package performance, reliability, and manufacturability, and conduct rigorous testing and validation of packaged systems.
• Create detailed design documentation, including engineering drawings, specifications, and test reports, and analyze test data to identify areas for improvement and optimize future designs.

Qualifications

• Advanced degree (Masters or Ph.D.) in Electrical Engineering, Mechanical Engineering, Applied Physics, or a related field.
• Proven industry experience in advanced packaging design, simulation, and development, with a strong understanding of packaging technologies, including flip-chip, wafer-level packaging, and 3D integration.
• Experience with high-speed interconnect technologies, such as silicon photonics and microelectronics, and packaging design and development for silicon photonics devices.

Current and past relevant companies include: AMD, Intel, Lightmatter, Broadcom, Mellanox, Cisco, Coherent, Macom, GlobalFoundries, and other Photonics/Optical startups