HBM SoC RTL Design Engineer for High Performance AI

Micron Technology, Inc; Richardson (TX); On-site; USD 121,000 - 247,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Bonuses and equity

Job summary

Micron Technology, Inc. is seeking a SoC Design Engineer in the Heterogeneous Integration Group to design RTL for HBM logic die, integrate IP, and collaborate across architecture, verification, and physical design teams.

You will participate in pre‑silicon validation and post‑silicon bring‑up, support timing and power goals, and help enable AI‑driven workflows. A strong background in SystemVerilog, RTL, and tools like Cadence/Synopsys is required.

Qualifications

• Bachelor’s or master’s degree in electrical or computer engineering with a minimum of 6 years of related experience.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with RTL-to-GDS flow including synthesis, static timing analysis, and sign-off considerations.

Responsibilities

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP and collaborate with SoC architects.
• Contribute to clocking, reset, power intent, and configuration infrastructure.
• Assist with pre-silicon validation and post-silicon bring-up, root-cause analysis.
• Document designs, participate in design reviews, and support manufacturing.

Skills

RTL design

SystemVerilog

Verilog

RTL integration

Python scripting

TB/verification familiarity

collaboration across teams

Education

Bachelor's or Master's in EE/CE

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology, Inc. is seeking a SoC Design Engineer in the Heterogeneous Integration Group to design RTL for HBM logic die, integrate IP, and collaborate across architecture, verification, and physical design teams.

You will participate in pre‑silicon validation and post‑silicon bring‑up, support timing and power goals, and help enable AI‑driven workflows. A strong background in SystemVerilog, RTL, and tools like Cadence/Synopsys is required.