Hardware Verification Engineer - High-Performance Silicon

River AI Inc.; Austin, Palo Alto (TX, CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, vision benefits

Unlimited PTO

Relocation support

Job summary

River AI Inc. is seeking a Member of Technical Staff, Hardware, Design Verification Engineer in Austin, TX or Palo Alto, CA. You will define test benches, develop UVM-based environments, and push verification of high-performance silicon.

Collaboration with RTL, performance modeling, and compiler teams is essential. The role requires 5+ years experience, strong SystemVerilog and UVM skills, and a deep understanding of CPU/GPU/SoC architectures.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering or Computer Science with 5+ years of industry experience.
• Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
• Expert command of SystemVerilog for verification, including OOP, randomization, and functional coverage.
• Strong understanding of computer architecture, pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (AXI, CHI).
• Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
• Collaborative mindset and bias for action to push boundaries and co-design with engineers.

Responsibilities

• Verification Strategy & Planning: Define verification plans from architectural specs for complex blocks.
• UVM Environment Development: Architect scalable, reusable test benches using SystemVerilog and UVM.
• Constrained-Random Testing: Develop complex sequences to achieve high functional coverage.
• Coverage-Driven Verification: Define functional coverage models and analyze code coverage.
• Formal Verification: Use SVA and formal methods to prove correctness where applicable.
• Emulation: Use ZeBu/HAPS and Palladium/Protium for scaled testing.
• Debug & Analysis: Debug failures with waveform viewers and work with RTL to fix issues.
• Automation & Scripting: Maintain regression flows using Python, Perl, Bash, or TCL.

Skills

UVM-based environments

SystemVerilog

OOP in SV

Algorithms & testing

Education

Bachelor's degree in EE/CS/CE

Tools

UVM

SystemVerilog

Job description

River AI Inc. is seeking a Member of Technical Staff, Hardware, Design Verification Engineer in Austin, TX or Palo Alto, CA. You will define test benches, develop UVM-based environments, and push verification of high-performance silicon.

Collaboration with RTL, performance modeling, and compiler teams is essential. The role requires 5+ years experience, strong SystemVerilog and UVM skills, and a deep understanding of CPU/GPU/SoC architectures.