Senior PD Methodology Engineer - ML Accelerator CAD Leader

Amazon; Austin (TX); On-site; USD 159,200 - 215,300; Full time

Job summary

Annapurna Labs, part of AWS Utility Computing, is seeking a senior physical design engineer to define, develop, and deploy PD/verification methodologies (RTL2GDS) for ML accelerator chips in advanced nodes.

You will drive CAD flow optimizations for PPA and TAT, work with EDA vendors, tune cloud infrastructure, and interface with RTL, PD, and DFT teams to improve efficiency and QoR dashboards.

Qualifications

• 10+ years in physical design or CAD flow development.
• Experience with RTL2GDS and advanced node flows.
• Strong scripting in Python/Perl and C++.

Responsibilities

• Define, develop, and deploy PD/verification methods (RTL2GDS) for ML accelerator chips.
• Drive CAD flow optimizations for PPA and TAT improvements.
• Work with EDA tool vendors to evaluate methods and fix issues.
• Fine-tune cloud infrastructure to improve compute/storage utilization for PD.
• Coordinate with RTL, PD, Package, and DFT teams to improve methods.
• Troubleshoot digital tool flows and deploy scalable solutions.
• Create dashboards and reports for QoR and project tracking.
• Fluent in TCL, Python; build scalable flows for parallel design.

Skills

Python

Perl

C++

Scripting

EDA collaboration

Education

BS + 10 years in EE/CS

MS + 7 years in EE/CS

Tools

Innovus

ICC2

Fusion Compiler

STA

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Job description

Annapurna Labs, part of AWS Utility Computing, is seeking a senior physical design engineer to define, develop, and deploy PD/verification methodologies (RTL2GDS) for ML accelerator chips in advanced nodes.

You will drive CAD flow optimizations for PPA and TAT, work with EDA vendors, tune cloud infrastructure, and interface with RTL, PD, and DFT teams to improve efficiency and QoR dashboards.