Hardware Design and Failure Analysis Engineer

Hallmark Global Solutions Ltd; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Hallmark Global Solutions Ltd in San Jose, CA is seeking a Hardware Design and Failure Analysis Engineer. The role requires a BS/MS in EE/CE/MSE with 10+ years of hardware engineering and system-level failure analysis, focusing on robust board design.

You will tackle PCIe Gen4/5/6, DDR4/5, HBM, SerDes, optical transceivers, and power/signal integrity issues, coordinating with external silicon suppliers and labs, and communicating findings to executives.

Qualifications

• 10+ years of hardware engineering, board design, or system-level failure analysis.
• PCIe Gen4/5/6, DDR4/5, HBM, SerDes, optical transceivers.
• Strong communication and cross-functional leadership.

Responsibilities

• Lead hardware failure analysis and root-cause investigations.
• Direct external silicon suppliers and analytical labs for FA.
• Communicate complex findings to executives and cross-functional teams.
• Lead hardware quality or reliability task forces for hyperscale cloud providers.

Skills

High-Speed Hardware Architecture

Power & Signal Integrity

Supplier Engagement

Communication to Executives

Python Automation

Education

B.S./M.S. in Electrical/Computer Engineering or related field

Tools

Python

C Programming

Job description

Title: Hardware Design and Failure Analysis Engineer

Location: San Jose CA (Onsite)

Education & Experience: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or related field with 10+ years of progressive experience in hardware engineering, board design, or system-level failure analysis.

High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).

Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies.

Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.

Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.

Preferred Qualifications

Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).

Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.

Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.

Skills:

• EIS : ASIC Ciruit Design - Analog and Mixed Signal IC Circuit design
• EIS : Thermal Analysis
• EIS : Embedded Digital Hardware Design and Development Experience Required: 6-8