Hardware Design Engineer

Hallmark Global Solutions Ltd; San Jose (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Hallmark Global Solutions Ltd in San Jose, CA is seeking an experienced Hardware Design & Failure Analysis Engineer to lead root-cause investigations and design validation for high-performance computing platforms. The role focuses on rapid debugging, reliability improvement, and collaboration across multiple engineering teams to ensure scalable, robust hardware.

The ideal candidate will own failure analysis from system level to silicon, drive corrective actions, and support large-scale

Qualifications

• Experience conducting hardware failure investigations from board to silicon level.
• Strong background in high-speed digital design and server/ASIC platforms.
• Ability to debug complex hardware issues including SI/PI and power delivery.

Responsibilities

• Lead hardware failure analysis investigations from system level down to component and silicon level.
• Analyze and debug complex hardware issues involving processor, memory, ASIC, FPGA, and board-level designs.
• Perform root cause analysis on field failures, manufacturing issues, and customer escalations.
• Investigate signal integrity and power integrity issues across high-speed interfaces.
• Collaborate with design, validation, quality, manufacturing, and supplier engineering teams.
• Drive corrective actions and design improvements based on failure analysis findings.
• Interface with external silicon vendors, component suppliers, and analytical laboratories for physical failure analysis activities.
• Develop and execute test methodologies to recreate intermittent or corner-case hardware failures.
• Present technical findings and recommendations to engineering leadership and enterprise customers.
• Support reliability, qualification, and hardware quality initiatives for large-scale deployments.

Skills

High-Speed HW Design

Failure Analysis

Signal Integrity

Power Integrity

System-level Debugging

Tools

Logic Analyzers

Oscilloscopes

Protocol Analyzers

Job description

Role: - Hardware Design & Failure Analysis Engineer

Location: Onsite/Hybrid San Jose CA

Job Summary

We are seeking an experienced Hardware Design & Failure Analysis Engineer to drive root cause investigations, hardware reliability improvements, and design validation activities for next-generation high-performance computing and data centre platforms. The ideal candidate will possess deep expertise in high-speed digital hardware design, failure analysis, signal integrity, power integrity, and system-level debugging across complex server and ASIC-based platforms.

Key Responsibilities

• Lead hardware failure analysis investigations from system level down to component and silicon level.


• Analyze and debug complex hardware issues involving processor, memory, ASIC, FPGA, and board-level designs.


• Perform root cause analysis on field failures, manufacturing issues, and customer escalations.


• Investigate signal integrity and power integrity issues across high-speed interfaces.


• Collaborate with design, validation, quality, manufacturing, and supplier engineering teams.


• Drive corrective actions and design improvements based on failure analysis findings.


• Interface with external silicon vendors, component suppliers, and analytical laboratories for physical failure analysis activities.


• Develop and execute test methodologies to recreate intermittent or corner-case hardware failures.


• Present technical findings and recommendations to engineering leadership and enterprise customers.


• Support reliability, qualification, and hardware quality initiatives for large-scale deployments.

Required Technical Skills

High-Speed Hardware Design

• Strong understanding of modern computing architectures and high-speed interfaces:


• DDR4 / DDR5


• HBM Memory


• 56G / 112G / 224G SerDes


• Optical Transceivers

Failure Analysis & Debug

• Board-level and system-level failure analysis


• Electrical characterization and debug


• Logic Analyzers

Power & Signal Integrity

• Power Distribution Network (PDN) analysis


• Multi-phase VRM design and transient response debugging


• PMBus and SVID telemetry analysis


• Switching noise characterization


• Signal Integrity (SI) and Power Integrity (PI) validation

Hardware Design Expertise

• Analog & Mixed Signal IC Circuit Design


• Embedded Digital Hardware Design & Development


• Thermal Analysis and Thermal Reliability Engineering


• ASIC and system-level hardware architecture