Graduate FPGA Engineer: Low-Latency Trading Systems

Optiver; Illinois; On-site; USD 180,000 - 220,000; Full time

Job summary

Optiver is seeking an FPGA Engineer to build nanosecond-accurate, highly parallelized hardware for a global trading firm. You’ll design with FPGAs/ASICs and collaborate with traders, software and infra teams to push latency boundaries.

Ideal candidates are pursuing a bachelor’s, master’s, or PhD in Computer or Electrical Engineering, expect to graduate between 2026-2027, and have hands-on HDL experience (VHDL/Verilog/SystemVerilog).

Qualifications

• A student pursuing a bachelor’s, master’s, or PhD in Computer Engineering or Electrical Engineering.
• On track to graduate between December 2026 to June 2027.
• Hands-on experience in digital design with FPGAs or ASICs.
• Experience writing hardware in VHDL, Verilog, or SystemVerilog.
• Passionate about clean code, well-architected systems and continuous improvement.
• Collaborative teammate with developers, traders and business teams.

Responsibilities

• Accelerate network infrastructure and trading system components with high-speed hardware designs.
• Research new low-latency techniques and platforms and identify integration opportunities.
• Collaborate in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware or in-house versions to ensure FPGAs interface with cutting-edge server hardware.

Skills

FPGA design

HDL development

Collaborative teamwork

Problem solving

Education

Bachelor's/Master's/PhD in Computer Engineering or Electrical Engineering

Tools

VHDL

Verilog

SystemVerilog

Job description

Optiver is seeking an FPGA Engineer to build nanosecond-accurate, highly parallelized hardware for a global trading firm. You’ll design with FPGAs/ASICs and collaborate with traders, software and infra teams to push latency boundaries.

Ideal candidates are pursuing a bachelor’s, master’s, or PhD in Computer or Electrical Engineering, expect to graduate between 2026-2027, and have hands-on HDL experience (VHDL/Verilog/SystemVerilog).