FPGA Engineer: Low-Latency Trading Hardware

Optiver; New York (NY); On-site; USD 180,000 - 220,000; Full time

Benefits offered by this job

Profit-sharing

Bonus

401(k) match

Health coverage

Office perks

Job summary

Optiver is seeking a Hardware Engineer to design and verify FPGA-based trading systems. You will contribute across the full development cycle, collaborating with traders, software engineers, and infra teams to deliver low-latency solutions.

The role requires hands-on experience with HDL (VHDL/Verilog/SystemVerilog) and C/C++, FPGA/ASIC design, and RTL synthesis. You will join a high-performance, globally distributed team focused on precise, efficient market making.

Qualifications

• A Bachelor’s degree in CE, EE, CS, or related technical field.
• Experience designing, coding, testing, and verifying FPGAs and/or ASICs.
• Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++.
• Experience with RTL synthesis, writing timing, area, and other relevant constraints.
• Experience with digital simulators and self-checking test benches.
• Ability to work closely with software developers to rapidly deliver integrated systems.

Responsibilities

• Accelerate network infrastructure and trading system components with high-speed hardware designs.
• Research new low-latency techniques and platforms and identify opportunities for integration with our trading system.
• Work in a multidisciplinary team of traders, software developers, and infrastructure engineers.
• Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware.
• Manage relationships with 3rd party vendors.

Skills

FPGA design

RTL design

SystemVerilog

Verilog

VHDL

C/C++

Tools

Verilog

VHDL

SystemVerilog

RTL synthesis

FPGAs

Job description

Optiver is seeking a Hardware Engineer to design and verify FPGA-based trading systems. You will contribute across the full development cycle, collaborating with traders, software engineers, and infra teams to deliver low-latency solutions.

The role requires hands-on experience with HDL (VHDL/Verilog/SystemVerilog) and C/C++, FPGA/ASIC design, and RTL synthesis. You will join a high-performance, globally distributed team focused on precise, efficient market making.