GPU PD Engineer: Shape Next-Gen High-Performance Chips

Apple Inc.

Austin (TX)

On-site

USD 180,000 - 240,000

Full time

14 days+

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Job summary

Apple Inc. is seeking a highly skilled engineer to contribute to silicon technology development for GPUs. You will work on design convergence, physical design optimization, and integration of complex RTL into tapeout-ready flows.

The role requires strong collaboration with FE teams and in-depth knowledge of PPA, timing, and signoff across modern nodes. This position targets candidates with hands-on experience in ASIC implementation and a passion for performance and efficiency.

Qualifications

  • Bachelor's degree in Engineering or CS required.
  • Experience or coursework in physical design, synthesis, DFT or clocking.
  • Experience or coursework with digital logic design, RTL, CMOS transistor logic or VLSI concepts.
  • Experience with scripting languages such as TCL, Python, Perl or shell scripting.

Responsibilities

  • Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.
  • Drive PD construction and optimization recipes for performance, power and area (PPA).
  • Work on pioneering designs in the latest technology nodes.
  • Collaborate to drive methodologies and best known methods to streamline PD work, guidelines, checklists, and execution.
  • Lead and resolve design and flow issues related to physical design and drive execution.

Skills

Physical design
Synthesis
DFT
Clocking
Digital logic design
RTL
CMOS transistor logic
VLSI concepts
Scripting languages

Education

Bachelor's degree in Engineering or Computer Science

Tools

EDA tools
APIs

Job description

Apple Inc. is seeking a highly skilled engineer to contribute to silicon technology development for GPUs. You will work on design convergence, physical design optimization, and integration of complex RTL into tapeout-ready flows.

The role requires strong collaboration with FE teams and in-depth knowledge of PPA, timing, and signoff across modern nodes. This position targets candidates with hands-on experience in ASIC implementation and a passion for performance and efficiency.

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