GPU Top Design Engineer

Socket.dev; Austin (TX); On-site; USD 180,000 - 230,000; Full time

Job summary

Apple in Austin, TX is seeking an experienced RTL/SoC design engineer to contribute to GPU power management and SOC interface logic. You will work with Platform Architecture, Software, and Design Verification teams to deliver RTL and specifications while integrating IP across teams.

The role emphasizes timing, power, and area optimization, collaboration across sites, and delivering design collateral to Physical Design teams to meet project milestones.

Qualifications

• BS/MS CE or EE required.
• Experience writing RTL in Verilog and/or SystemVerilog.
• Experience with logic synthesis, timing analysis and floor planning.

Responsibilities

• Deliver RTL design collateral and interfaces to Physical Design teams.
• Assess and integrate IP from other teams.
• Close timing, power, area, and lint for design by optimizing RTL and constraints.
• Drive performance, power, area targets for SOC designs.
• Provide schedules to IP teams and management.
• Collaborate with IP teams across multiple sites.

Skills

RTL design

Verilog/SystemVerilog

Logic optimization

Synthesis

Timing analysis

Floor planning

Power intent descriptions

Clock domain crossings

Education

BS/MS in CE or EE

Job description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see theimportance in every detail? As part of our Silicon Technologies group, you’ll help design and manufactureour next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensureApple products and services can seamlessly and expertly handle the tasks that make them beloved bymillions. Joining this group means you’ll be responsible for crafting and building the technology that fuelsApple’s devices. Together, you and your team will enable our customers to do all the things they lovewith their devices! At Apple, we push our designs to the limit in order to make amazing products. Wewant to delight our customers with hardware that performs great while delivering long battery life. Aspart of the mobile GPU design team, you will collaborate with Platform Architecture, Software, DesignVerification, and Physical Design teams to deliver RTL and specifications for GPU power management andSOC interface logic. In addition, you will be responsible for integrating applicable IP from other teams toenable complete security, debug, and power management solutions!

Description

• Deliver high quality design collateral, including RTL, to Physical Design teams
• Assess and integrate IP from other Apple teams
• Close timing, power, area, and lint for design by optimizing RTL and constraints
• Drive performance, power, area, and functional goals
• Provide schedules to IP teams and management
• Collaborate effectively with IP teams spanning multiple sites

Minimum Qualifications

• BS/MS CE or EEExperience in one or more of the following areas: logic optimization, synthesis, timinganalysis, floor-planning, power intent descriptions, and clock domain clock crossings
• Experience writing RTL in Verilog and/or System Verilog
• Experience with logic simulation and debug

Preferred Qualifications

• Ability to write one or more scripting languages
• Experience in Graphics hardware design
• Experience in power management for large designs like CPUs, GPUs, or SOCs