GPU Physical Design Engineer

Apple Inc.; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. in Santa Clara, CA seeks a Senior Physical Design engineer to drive chip integration from RTL to tapeout, collaborating with FE teams to optimize floorplanning and PD flow.

This role centers on delivering high-performance, power-efficient GPU designs by advancing Synthesis, DFT, Clock and Power distribution, and all aspects of timing, electrical and physical signoff.

Qualifications

• BS + 3 years of relevant experience.
• Experience with floorplanning partitions, routing and placement flow experiments, reviewing static timing, and physical design verification flow results.

Responsibilities

• Drive PD construction and optimization for performance, power and area (PPA).
• Collaborate with FE teams to understand chip architecture and influence floorplanning early in design.
• Lead and resolve design and flow issues related to physical design and drive execution.
• Coordinate to drive IP integration from internal and external vendors in the physical domain.
• Guidance on methodologies and best practices to streamline PD work and set checklists.

Skills

Floorplanning

Place & Route

Static Timing Analysis

Physical Design Verification

RTL to Tapeout

Education

Bachelor's degree in Electrical Engineering or related

Tools

Synthesis

DFT insertion

Clock distribution

Job description

Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions! Joining this group means crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to tapeout.

Description

• Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle.
• Drive outstanding PD construction and optimization recipes for performance, power and Area (PPA).
• Work on pioneering designs in the latest technology nodes.
• Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress.
• Drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR.
• Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution.

Minimum Qualifications

• BS + 3 years of relevant experience.
• Experience with one or more of the following: floorplanning partitions, conducting route and placement flow experiments, reviewing static timing, and physical design verification flow results.

Preferred Qualifications

• We value ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
• Work with FE teams to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback.
• Use design knowledge and innovative physical construction and optimization flows to push performance, power, and Area (PPA) of GPU designs.
• Experience with multi-voltage, power gated, and power retention will be an advantage.
• Practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset.
• Experience on integrating IP from both internal and external vendors and able to specify and drive IP requirements in the physical domain.
• Depth of expertise with large GPU designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies.
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal management.

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