GAAFET FEOL Module Integration Engineer (2nm)

Samsung Semiconductor; Austin (TX); On-site; USD 95,000 - 120,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Life insurance and 401(k) matching

Onsite café(s) and workout facilities

Paid maternity and paternity leave

PTO + holidays

Job summary

Samsung Austin Semiconductor seeks a Module Integration Engineer to join the 2nm GAAFET program. You will bridge unit process development and device performance, focusing on RPMG and CTSDB modules within FEOL.

You will collaborate across lithography, etch, deposition, and device physics to ensure reliable gate stack and contact integration for the next generation of computing. The role requires DOE studies, data analysis, and cross-functional reviews with Device and Layout teams to ensure

Qualifications

• Master’s degree required (industry experience possible).
• PhD preferred in related field.
• 2–3 years of experience preferred but not required.

Responsibilities

• Module Ownership: support integration/optimization of RPMG and CTSDB modules.
• Process Integration: collaborate with Etch, CVD, ALD, CMP, Litho engineers.
• DOE studies to evaluate process variation impact on electrical performance.
• Failure Analysis using TEM/SEM/AFM/EDX to identify root causes and corrective actions.
• Analyze large datasets with statistical tools to correlate parameters with yield.
• Participate in design reviews with Device and Layout teams to ensure manufacturability.

Skills

Python

R

SQL

Education

Master's degree in Materials Science, Chemistry, Physical Chemistry, or Physics

Ph.D. in Materials Science, Chemistry, Physical Chemistry, or Physics (preferred)

Tools

Spotfire

Minitab

Job description

Samsung Austin Semiconductor seeks a Module Integration Engineer to join the 2nm GAAFET program. You will bridge unit process development and device performance, focusing on RPMG and CTSDB modules within FEOL.

You will collaborate across lithography, etch, deposition, and device physics to ensure reliable gate stack and contact integration for the next generation of computing. The role requires DOE studies, data analysis, and cross-functional reviews with Device and Layout teams to ensure