Full‑Chip HBM SoC Verification Engineer

Micron Technology, Inc; Richardson (TX); On-site; USD 97,000 - 205,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Equity

Job summary

Micron Technology seeks a Physical Verification Engineer for the Heterogeneous Integration Group in Richardson, TX. You will own full‑chip PV sign‑off, collaborating across design, EDA, and foundry teams to deliver tape‑out ready silicon under aggressive schedules.

You’ll work on DRC/LVS/ERC/DFM, antenna checks, reliability sign‑off, and ML‑assisted PV tools, with opportunities to influence process nodes from 3nm and below. Strong scripting is valued.

Qualifications

• Experience with full‑chip or block‑level physical verification for advanced nodes.
• Experience in PV methodologies: DRC, LVS, ERC, PERC, DFM, antenna, reliability sign‑off.

Responsibilities

• Implement PV sign‑off for full‑chip and hierarchical designs (DRC/LVS/ERC/PERC/DFM).
• Debug and manage foundry rule decks, waivers, and clean closure per advanced‑node requirements.
• Perform reliability verification across power domains (ESD, latch‑up, electromigration).
• Run density, metal fill, CMP checks for yield awareness at 3nm and below.
• Perform RC extraction and correlate PV results with post‑silicon measurements.
• Develop and optimize PV flows, automation, and regression infrastructure (Python/Tcl/Perl).
• Support AI/ML based PV tools and PPA optimization.
• Collaborate with design, CAD, RTL, EDA, and foundry teams including TSMC from kick‑off to tape‑out.

Skills

DRC

LVS

ERC

DFM

Python scripting

Tcl scripting

Perl scripting

AI/ML PV

Education

Master’s or PhD in Electrical/Computer Engineering

Tools

Calibre

IC Validator (ICV)

Pegasus

Job description

Micron Technology seeks a Physical Verification Engineer for the Heterogeneous Integration Group in Richardson, TX. You will own full‑chip PV sign‑off, collaborating across design, EDA, and foundry teams to deliver tape‑out ready silicon under aggressive schedules.

You’ll work on DRC/LVS/ERC/DFM, antenna checks, reliability sign‑off, and ML‑assisted PV tools, with opportunities to influence process nodes from 3nm and below. Strong scripting is valued.