Senior Physical Design Engineer

Espace; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Competitive salaries

Health and wellness care options

Paid time off

Job summary

Espace is seeking a Senior Physical Design Engineer to join our ASIC implementation team in Saratoga, California. This full-time role involves leading the physical design of complex SoCs for IoT and satellite communications.

The ideal candidate will have 8+ years of experience, deep expertise in Cadence Innovus, and a strong background in scripting and physical verification. The position offers a competitive salary within the range of $120,000 to $220,000 annually.

Join us to make a difference and work in an innovative environment focused on sustainability.

Qualifications

• Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs.
• Deep expertise in Cadence Innovus and familiarity with other P&R tools.
• Strong experience in floorplanning, power planning, placement, CTS, and routing for multi-million gate designs.

Responsibilities

• Lead physical design implementation from floorplanning through GDSII sign-off.
• Drive physical design closure meeting PPA targets.
• Develop and maintain physical design scripts, flows, and automation.

Skills

Cadence Innovus

Digital ASICs design

Tcl scripting

Python scripting

Floorplanning

Power planning

Signal integrity analysis

Tools

Mentor Calibre

Synopsys ICC2

Synopsys ICV

Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E‑Space is bridging Earth and space to enable hyper‑scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly‑advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space‑based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation team. In this role, you will be responsible for the physical implementation of complex digital SoC designs from netlist to GDSII, targeting advanced process nodes for 5G, IoT, and LEO satellite communications applications. You will work closely with front‑end design, verification, and timing teams to deliver high‑quality, performance‑optimized silicon.

Responsibilities

• Lead physical design implementation from floorplanning through GDSII sign-off for complex SoC blocks and full‑chip designs
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), and routing
• Drive physical design closure meeting PPA (Power, Performance, Area) targets across all design corners
• Collaborate with the STA team to analyze and resolve timing violations through ECO‑driven optimization
• Conduct and resolve physical verification (DRC, LVS, ERC) issues in partnership with the sign‑off team
• Develop and maintain physical design scripts, flows, and automation in Tcl/Python
• Work with foundry process design kits (PDKs) and ensure design rule compliance on advanced nodes
• Support integration of hard macros, memory compilers, and analog IP into top‑level designs
• Analyze and optimize signal integrity, including crosstalk and noise effects
• Contribute to physical design methodology development and mentor junior engineers

Qualifications

• Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs
• Deep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2
• Strong experience in floorplanning, power planning, placement, CTS, and routing for multi‑million gate designs
• Deep knowledge of timing‑driven physical design and working with STA engineers for timing closure
• Experience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debug
• Proficiency in scripting (Tcl, Python) for flow development and automation
• Solid understanding of low‑power design techniques (clock gating, power domains, UPF/CPF)
• Experience with advanced process nodes and associated PDK constraints
• Strong problem‑solving skills and attention to detail in a deadline‑driven environment
• Experience with 7nm or sub‑7nm process nodes
• Exposure to custom digital or mixed‑signal IC physical design
• Familiarity with signal integrity analysis tools and methodology
• Experience with hierarchical physical design flows for very large SoCs
• Background in satellite, 5G, or IoT chip design

This is a full‑time, exempt position, based out of our Saratoga office. The target base pay for this position is $120,000–$220,000 annually. The total compensation package will be determined by various factors such as your relevant job‑related knowledge, skills, and experience.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Benefits

• An opportunity to really make a difference
• Sustainability at our core
• Fair and honest workplace
• Innovative thinking is encouraged
• Competitive salaries
• Continuous learning and development
• Health and wellness care options
• Financial solutions for the future
• Optional legal services (US only)
• Paid holidays
• Paid time off