FPGA Verification Engineer III – Lunar Permanence

Jobtailor; Town of Florida (NY); On-site; USD 150,000 - 190,000; Full time

Job summary

Blue Origin is seeking an FPGA verification engineer to drive verification strategy for high-reliability avionics used in the Human Landing System. You will craft UVM-based verification environments, develop testbenches, and write directed and random test cases to achieve coverage goals.

You will document plans, run regressions, and report coverage matrices while collaborating with the FPGA team to ensure safety-critical compliance and integration with HW/SW interfaces.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or a closely related field of study.
• 5+ years of experience verifying FPGAs or ASICs.
• In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent.
• In-depth knowledge of SystemVerilog and Universal Verification Methodology (UVM).
• Expertise developing testbench environments and verification components from scratch, including Monitor, Scoreboard, Driver, and Agent.
• Understanding of coverage types, cover classes, and cover points.
• Experience with predictive testbench components, functional coverage, and assertions.
• Experience with constrained-random verification.
• Experience with the Register Abstraction Layer.
• Experience developing detailed test plans, writing tests, running regressions, collecting coverage matrices, and reporting progress.
• Experience reviewing verification and validation results against coverage goals.
• Experience writing, analyzing, and achieving coverage metrics.
• Debugging skills to isolate issues between RTL design and testbench or test case.
• Passion for Blue Origin’s mission and vision.
• U.S. citizenship or nationality, U.S. permanent residency, or lawful admission to the U.S. as a refugee or asylee.
• Familiarity with AXI protocols, PCIe, Ethernet, SPI, or I2C interfaces is helpful.
• Experience debugging FPGA/ASIC hardware and assisting with HW/SW integration is helpful.
• Experience managing regression and continuous integration infrastructure within GitLab is helpful.
• Knowledge of Python, Perl, or TCL/Shell scripting is helpful.
• Working knowledge of NPR 7150.2, DO-254, or another safety-critical software standard is helpful.

Responsibilities

• Verify FPGAs or ASICs using UVM and SystemVerilog.
• Develop comprehensive verification and validation plans for functional and system-level verification.
• Develop IP-, subsystem-, and system-level testbenches and tests to meet coverage goals.
• Document plans and procedures and write directed and random test cases.
• Generate reports supporting certification of high-DAL designs.
• Develop test plans, run regressions, collect coverage matrices, and report progress to the program.
• Review verification and validation results against coverage goals and metrics.
• Debug issues between RTL design and testbench or test cases.
• Collaborate within the FPGA team to build high-reliability avionics solutions for Blue Origin’s Human Landing System.

Skills

FPGA verification

UVM

SystemVerilog

Testbench Development

Coverage Metrics Analysis

Constrained-Random Verification

Debugging RTL Design

Test Plan Development

Regression Testing

Hardware/Software Integration

RTL Simulation

Education

BS/MS in Electrical Engineering, Computer Engineering, or related field

Tools

Siemens QuestaSim

ModelSim

GitLab

Python

Perl

TCL/Shell Scripting

Job description

• Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM)


• Create comprehensive verification and validation plans covering functional- and system-level verification and validation


• Develop IP-, subsystem-, and system-level testbenches and tests to achieve coverage goals


• Document plans and procedures


• Write directed and random test cases


• Generate reports supporting certification of high-DAL designs


• Develop detailed test plans, run regressions, collect coverage matrices, and report progress to the program


• Review verification and validation results against coverage goals


• Write, analyze, and achieve coverage metrics


• Debug issues between RTL design and testbench or test cases


• Collaborate within the FPGA team to build high-reliability, safety-critical avionics solutions for Blue Origin’s Human Landing System vehicle

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or a closely related field of study


• 5+ years of experience verifying FPGAs or ASICs


• In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent


• In-depth knowledge of SystemVerilog and Universal Verification Methodology (UVM)


• Expertise developing testbench environments and verification components from scratch, including Monitor, Scoreboard, Driver, and Agent


• Understanding of coverage types, cover classes, and cover points


• Experience with predictive testbench components, functional coverage, and assertions


• Experience with constrained-random verification


• Experience with the Register Abstraction Layer


• Experience developing detailed test plans, writing tests, running regressions, collecting coverage matrices, and reporting progress


• Experience reviewing verification and validation results against coverage goals


• Experience writing, analyzing, and achieving coverage metrics


• Debugging skills to isolate issues between RTL design and testbench or test case


• Passion for Blue Origin’s mission and vision


• U.S. citizenship or nationality, U.S. permanent residency, or lawful admission to the U.S. as a refugee or asylee


• Ability to pass the required Blue Standard Background Check


• Familiarity with AXI protocols, PCIe, Ethernet, SPI, or I2C interfaces is helpful


• Experience debugging FPGA/ASIC hardware and assisting with HW/SW integration is helpful


• Experience managing regression and continuous integration infrastructure within GitLab is helpful


• Knowledge of Python, Perl, or TCL/Shell scripting is helpful


• Working knowledge of NPR 7150.2, DO-254, or another safety-critical software standard is helpful

Core Competencies

Demonstrates expertise in FPGA verification using Universal Verification Methodology (UVM) and SystemVerilog, with a strong focus on developing comprehensive test plans and achieving coverage goals. Proficient in debugging RTL designs and collaborating within teams to deliver high-reliability avionics solutions.

Highest-signal resume keywords

• FPGA Verification


• Universal Verification Methodology (UVM)


• SystemVerilog


• RTL Simulation Tools


• Testbench Development

Hard Skills

• FPGA Verification


• SystemVerilog


• Universal Verification Methodology (UVM)


• Testbench Development


• Coverage Metrics Analysis


• Constrained-Random Verification


• Debugging RTL Design


• Test Plan Development


• Regression Testing


• Hardware/Software Integration

Soft Skills

• Collaboration


• Communication

Industry Keywords

• High-DAL Designs


• Safety-Critical Standards


• NPR 7150.2


• DO-254


• AXI Protocols


• PCIe


• Ethernet


• SPI


• I2C

Tools & Technologies

• Siemens QuestaSim


• ModelSim


• GitLab


• Python


• Perl


• TCL/Shell Scripting