FPGA RTL Engineer – DoD Clearance Eligible, Hybrid Raleigh

0 Base Design LLC; Raleigh (NC); Hybride; USD 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Restricted Stock and Options

401(k)

Health insurance

Paid time off

401(k) matching

Résumé du poste

0 Base Design LLC in Raleigh, NC is seeking a Mid-Level FPGA/RTL Design Engineer with 4 to 5+ years to own design, implementation, and verification for FPGA platforms (Xilinx and Lattice). You will write RTL in Verilog and VHDL across architecture, simulation, synthesis, timing closure and hardware bring-up.

The role emphasizes lab-based debugging, hardware/software integration, and collaboration with embedded software engineers; hybrid schedule with up to 2 days remote; DoD Secret clearance

Qualifications

• Minimum 4–5+ years of RTL design experience in Verilog and VHDL.
• Proven track record with Xilinx and Lattice FPGA families.
• Strong understanding of clock domain crossing and timing closure.
• Experience with testbenches and functional simulations.
• Lab-based debugging, hardware/software integration, and JTAG tools.
• Knowledge of high-speed interfaces (PCIe, SERDES, DDR, SPI, I2C, Ethernet).

Responsabilités

• RTL Design & Implementation: Design and implement digital logic in Verilog and VHDL for FPGA-based systems, targeting Xilinx and Lattice device families.
• Verification: Develop testbenches and perform functional simulation to validate design before hardware bring-up.
• Synthesis & Timing Closure: Drive designs through synthesis, place-and-route, and timing closure using Vivado and Lattice toolchains.
• Hardware/Software Integration: Collaborate with embedded software engineers to define hardware-software interfaces and support firmware bring-up.
• Hardware Bring-up & Debug: Lead lab-based debugging using ILAs, logic analyzers, oscilloscopes, and JTAG tools.

Connaissances

RTL Design

Digital Logic

FPGA

Embedded C/C++ familiarity

Verilog

VHDL

Formation

Bachelor of Science in Electrical Engineering or Computer Engineering

Outils

Vivado

Lattice Diamond/Radiant

Lattice Propel

Description du poste

0 Base Design LLC in Raleigh, NC is seeking a Mid-Level FPGA/RTL Design Engineer with 4 to 5+ years to own design, implementation, and verification for FPGA platforms (Xilinx and Lattice). You will write RTL in Verilog and VHDL across architecture, simulation, synthesis, timing closure and hardware bring-up.

The role emphasizes lab-based debugging, hardware/software integration, and collaboration with embedded software engineers; hybrid schedule with up to 2 days remote; DoD Secret clearance