FPGA Engineer — SDR & EW Platforms

Anduril Industries; Costa Mesa (CA); Sur place; USD 146 000 - 194 000; Plein temps

Avantages offerts par ce poste

Equity grants

Comprehensive benefits

Résumé du poste

Anduril Industries, a defense technology leader, seeks an FPGA Engineer in Costa Mesa, CA to lead end‑to‑end design and verification on AMD/Xilinx SOC/FPGA platforms for software defined radio systems. You will own HDL development, collaborate with cross‑discipline teams, and drive robust design processes to deliver mission‑ready electronics.

The role focuses on VHDL/Verilog, FPGA architecture, and AMD/Xilinx workflows, with opportunities to shape next‑gen EW platforms while operating in a

Qualifications

• 4–7 years professional experience.
• Experience with FPGA devices from major vendors (AMD/Xilinx, Altera/Intel).
• Proficient in HDL design using VHDL and/or Verilog.
• Proficiency in a Linux development environment.
• Ability to obtain and maintain an active U.S. Secret security clearance.
• Strong communication and self-starting mindset.

Responsabilités

• Own FPGA development for software defined radio platforms enabling EW functions.
• Collaborate with software and electrical engineers to bring up state of the art boards.
• Design and test VHDL DSP modules and infrastructure.
• Integrate subsystems into larger FPGA cores and resolve resource/timing contentions.
• Develop drivers for custom RF component boards (PLLs, front ends).
• Manage project deliverables and document progress.

Connaissances

FPGA development

HDL design

VHDL/Verilog

C

Python

Linux

Git/CI

Security clearance eligibility

Communication

Description du poste

Anduril Industries, a defense technology leader, seeks an FPGA Engineer in Costa Mesa, CA to lead end‑to‑end design and verification on AMD/Xilinx SOC/FPGA platforms for software defined radio systems. You will own HDL development, collaborate with cross‑discipline teams, and drive robust design processes to deliver mission‑ready electronics.

The role focuses on VHDL/Verilog, FPGA architecture, and AMD/Xilinx workflows, with opportunities to shape next‑gen EW platforms while operating in a