FPGA Engineer Engineer (eInfochips)

Arrow Components; California (MO); On-site; USD 100,000 - 130,000; Full time

Job summary

Arrow Components is seeking an FPGA Engineer to be based in San Jose, CA or Austin, TX. The ideal candidate will have at least 5 years of experience in Verilog design and be proficient in various EDA tools. Responsibilities include providing excellent customer satisfaction while collaborating with clients and reporting progress.

This position demands strong skills in scripting languages like Python and experience with high speed PCIe designs. Candidates must be comfortable working onsite at Arrow Client locations as required.

Qualifications

• At least 5+ years of experience in Verilog Design.
• Good understanding of RTL Design and Digital concepts.
• Ability to write scripts using Python, Tcl, Perl.

Responsibilities

• Proficient in Verilog/System Verilog coding constructs.
• Experience with industry standard interface protocols.
• Ensure customer satisfaction and report on progress.

Skills

Verilog/System Verilog coding

EDA tools

Scripting (Python, Tcl, Perl)

High speed PCIe designs

Static Timing Analysis

Industry standard interface protocols

Tools

VCS

Fusion Compiler

Questa CDC

Job description

FPGA Engineer (eInfochips)

Location: San Jose, CA and Austin, TX (Day-1 Onsite)

What Candidate Will Be Doing

• Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Experience with high speed PCIe designs and protocols.
• Experience with Industry standard interface protocols such as AXI, APB, etc.
• Experience with ARM Fabric IPs.
• Experience with IPXACT.
• Understanding of Computer Architecture fundamentals.
• Ability to write scripts using Python, Tcl, Perl etc.
• Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
• Proficiency with UPF (Low power intent)
• Proficiency in clock crossing techniques.
• Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.

What We Are Looking For

• Good in understanding RTL Design and Digital concepts
• Strong experience with EDA tools: Fusion Compiler, CDC
• Scripting: Pearl, Python, TCL
• At-least 5+ years of experience in Verilog Design
• AMBA AXI bus along-with ARM or C based processor
• Ensure customer satisfaction.
• Reporting to customers on daily or weekly progress effectively

Work Arrangement Fully Onsite: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

EEO Statement

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.