ASIC Design Engineer (eInfochips)

Arrow Electronics; Mountain View (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Arrow Electronics is seeking an ASIC Design Engineer for their Mountain View, CA location. The ideal candidate will have extensive experience in Verilog design, Fusion Compiler, and scripting in Python or Tcl.

This role requires a deep understanding of EDA tools and digital concepts. As a full-time position, applicants must be prepared for onsite work, potentially requiring travel to client offices. Join Arrow to contribute to exciting semiconductor design projects.

Qualifications

• At least 5+ years of experience in Verilog design.
• Proficient in clock crossing techniques.
• Experience with high speed PCIe designs.

Responsibilities

• Design and implement ASIC designs meeting specifications.
• Write and maintain scripts in Python, Tcl, Perl.
• Review and verify design specifications and implement corrections.

Skills

Verilog/SystemVerilog coding constructs

Scripting with Python, Tcl, Perl

EDA tools: Fusion Compiler, CDC

Understanding of RTL design

Knowledge of static timing analysis

Tools

VCS

Design Compiler

Spyglass Lint

Questa CDC

Genus

Job description

Location

Mountain View, CA (Remote)

Position

ASIC Design Engineer (eInfochips)

Job Description

Role: ASIC Design Engineer
Location: Mountain View, CA (Remote)
Note: Seeking candidate with Fusion Compiler and scripting experience.

What Candidate Will Be Doing

• Proficient in Verilog/SystemVerilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, connectivity tools, CDC checkers, low power static checkers, linting).
• Experience with high speed PCIe designs and protocols.
• Experience with industry standard interface protocols such as AXI, APB, etc.
• Experience with ARM Fabric IPs.
• Experience with IPXACT.
• Understanding of computer architecture fundamentals.
• Ability to write scripts using Python, Tcl, Perl etc.
• Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
• Proficiency with UPF (low power intent).
• Proficiency in clock crossing techniques.
• Knowledge of static timing analysis and understanding of timing signoff fundamentals.

What We Are Looking For

• Good understanding of RTL design and digital concepts.
• Strong experience with EDA tools: Fusion Compiler, CDC.
• Scripting: Perl, Python, Tcl.
• At least 5+ years of experience in Verilog design.
• Experience with AMBA AXI bus along-with ARM or C based processor.
• Ensure customer satisfaction.
• Reporting to customers on daily or weekly progress effectively.

Work Arrangement

Fully onsite: Must be able to travel to an Arrow client office location as requested by Arrow client leadership.

About eInfochips

eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. With over two decades of experience, more than 500 products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations across multiple verticals. Strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft, and Google. Along with Arrow’s $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients. Visit www.einfochips.com for our portfolio of product engineering services across various industries and verticals.

EEO Statement

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.

Job Details

Time Type: Full time. Job Category: Engineering Services.