Physical Design Engineer II (eInfochips Inc)

Arrow Components; California (MO); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

401(k) matching

Disability insurance

HSA/HRA options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Job summary

eInfochips, an Arrow company, is seeking a Physical Design Engineer II for on-site work in San Jose, CA. The role focuses on ASIC implementation, ensuring design goals are met in a fast-paced environment.

You will lead synthesis, PNR, and timing tasks while collaborating with RTL, architects, and DFT teams to drive signoff and quality. A strong background in EDA tools and scripting is required.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent).
• 7+ years of hands-on experience in physical design and implementation, including synthesis, PnR, timing convergence, and physical verification.
• Proficiency with EDA tools such as Innovus, Tempus, and Quantus; strong understanding of physical design flows.

Responsibilities

• Execute synthesis, PNR, and STA for ASIC partitions within strict schedules and goals.
• Collaborate with architects, RTL designers, and DFT engineers to resolve issues across blocks.
• Close EM/IR, drive LEC and physical verification signoff with methodology owners.
• Partner with design teams to address physical design challenges and enable efficient iteration.
• Refine implementation methodologies including EMIR, PDN, and TCL-driven flows.
• Troubleshoot flow issues and coordinate with EDA vendors as needed.

Skills

TCL scripting

EDA tool knowledge

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Tools

Innovus

Tempus

Quantus

Job description

Position

Physical Design Engineer II (eInfochips Inc)

Job Description

What You’ll Be Doing:

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

What We Are Looking For:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands‑on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence, and physical verification.
• Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, and a deep understanding of physical design flows and methodologies.

Preferred Qualifications:

• 7+ years of experience in physical design roles and related activities.
• Proven ability to adhere to tight schedules and implement low‑power design techniques.
• Experience in System‑on‑Chip (SoC) design and implementation.
• Expertise in sub‑7nm node technologies.
• Familiarity with industry‑standard EDA tools and their capabilities.
• Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

What’s In It For You:

• At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That’s why we offer competitive financial compensation, including various compensation plans and a solid benefits package.
• Medical, Dental, Vision Insurance
• 401(k) with Matching Contributions
• Short‑Term/Long‑Term Disability Insurance
• Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
• Paid Time Off (including sick, holiday, vacation, etc.)
• Tuition Reimbursement
• Growth Opportunities
• And more!

Arrangement: Fully On‑Site. Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location: Complete On‑Site at San Jose, CA.

About eInfochips

eInfochips, an Arrow company (Fortune #133), is a leading global provider of product engineering and semiconductor design services. With over two decades of experience, more than 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. eInfochips has strategic technology partnerships with Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft and Google to name a few.

EEO Statement

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy).

All Arrow job postings are for existing job vacancies. We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.