FPGA Engineer

Owen Daniels; Chandler (AZ); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

3 weeks vacation

1 week personal

1 week sick leave

10 holidays (T4 Staff level)

full medical/dental/vision

Job summary

Owen Daniels is seeking a Senior FPGA Engineer to lead FPGA SoC development for satellite communications. You will design, integrate IP, and debug high-performance RTL for space-grade platforms, leveraging AMBA AXI/APB, PCIe, and Gigabit transceivers.

Ideal candidates have 5+ years in FPGA/SoC design, hands-on with Xilinx Vivado and Altera Quartus, and strong experience with simulation tools such as ModelSim or QuestaSim. US citizenship is required.

Qualifications

• BS in EE, CS, or equivalent; 5+ years' industry experience.
• FPGA design in VHDL/SystemVerilog; FPGA/ASIC SoC design experience.
• Strong hands-on with Xilinx Vivado and Altera Quartus; simulation in ModelSim/QuestaSim.
• SoC debug with AMBA AXI/APB interfaces; fmax-optimized IP.
• RTL simulation, Static Timing Analysis, and SDC.

Responsibilities

Skills

FPGA design (VHDL/SystemVerilog)

SoC design experience

AMBA AXI/APB interfaces

AXI-Stream IP

RTL simulation

Synthesis and STA (Timing)

Gigabit transceivers (PCIe/1000BASE-X)

Ethernet TCP/IP

Embedded C/C++

Git

Embedded Linux (bonus)

Education

BS in EE, CS, or equivalent

Tools

Xilinx Vivado

Altera Quartus

ModelSim/QuestaSim

Job description

FPGA Engineer — Satellite & Space Technologies

Location: Arizona, USA

Salary: $120,000–$170,000/yr

US Citizen required

Company Overview and Role

A global leader in Satellite and Space technology is hiring an FPGA Engineer to join their Platforms and FPGA SoC Group. You'll lead the design, development, and debug of complex FPGA SoC systems for satellite communications — from IP integration through high-performance RTL and firmware. The ideal FPGA Engineer will need be experience level at Senior with at least 5 years experience.

What you'll bring

• BS in EE, CS, or equivalent; 5+ years' industry experience
• FPGA design in VHDL/SystemVerilog; FPGA/ASIC SoC design experience
• Strong hands-on with Xilinx Vivado and Altera Quartus; simulation in ModelSim/QuestaSim
• SoC debug experience with AMBA AXI/APB interfaces; fmax-optimized, pipelined AXI-Stream IP
• RTL simulation, Static Timing Analysis, and SDC
• At least one Gigabit transceiver protocol (PCIe, Interlaken, USB SuperSpeed, 1000BASE-X/SGMII, 10/40/100GBASE-R)
• Network protocol experience (Ethernet L1/L2/L3, IPv4/IPv6, TCP/UDP); VITA 49.2/DIFI or eCPRI a strong plus
• Embedded C/C++, microcontrollers, Git
• Bonus: Embedded Linux (Kernel/Yocto/U-Boot/DeviceTree), schematic capture/PCB debug
• Industry background in Satellite, Space, or Wireless preferred

Benefits

• 3 weeks vacation
• 1 week personal
• 1 week sick leave
• 10 holidays (T4 Staff level)
• full medical/dental/vision
• and more