FPGA DSP Engineer (RF/Communications)

KBR Careers; Beavercreek (OH); On-site; USD 115,000 - 150,000; Full time

Job summary

KBR in Beavercreek, OH is seeking an FPGA Engineer to design, develop, integrate, and test FPGA‑based DSP and communications systems. You will work hands‑on in a lab environment with real hardware and collaborate across hardware, firmware, and software teams.

The role emphasizes FPGA DSP implementations, performance tuning, verification, and contributing to system‑level integration. A bachelor’s in EE/CE, 4–7 years, VHDL/Verilog and Vivado experience are expected; DoD clearance is a plus, and US

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 4–7 years of relevant FPGA, DSP, communications, or signal processing experience.
• Proficiency in VHDL and/or Verilog.
• Experience with FPGA development tools such as Vivado (or similar).

Responsibilities

• Design, implement, and maintain FPGA‑based DSP logic for communications and RF systems.
• Implement and debug real‑time DSP algorithms in hardware, including filtering, FFTs, modulation/demodulation, and synchronization functions.
• Integrate FPGA designs with embedded processors and system interfaces using AXI.
• Develop supporting software and firmware to command and interface with FPGA modules.
• Assist with hardware bring‑up, integration, testing, and debugging in laboratory environments.

Skills

FPGA design

DSP concepts

VHDL/Verilog

Vivado

Linux development

Git

DoD security clearance

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

MATLAB/Simulink

Verilog/VHDL simulators

Job description

KBR in Beavercreek, OH is seeking an FPGA Engineer to design, develop, integrate, and test FPGA‑based DSP and communications systems. You will work hands‑on in a lab environment with real hardware and collaborate across hardware, firmware, and software teams.

The role emphasizes FPGA DSP implementations, performance tuning, verification, and contributing to system‑level integration. A bachelor’s in EE/CE, 4–7 years, VHDL/Verilog and Vivado experience are expected; DoD clearance is a plus, and US