FPGA Design Engineer – Data Center Networking & Equity

Arista Networks; Roseville (CA); Presencial; USD 110 000 - 170 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health insurance

Resumo da oferta

Arista Networks is seeking a Hardware Design Engineer to drive FPGA development for high-speed networking platforms in the Bay Area. You will own RTL/verification for the control path, collaborate with cross-functional hardware, software, and manufacturing teams, and push designs from concept through production.

The role emphasizes hands-on Verilog/SystemVerilog RTL coding, on-chip bus interfaces, and end-to-end FPGA flow, including timing closure and lab validation.

Qualificações

• 5+ years of hands-on Verilog/SystemVerilog RTL design experience.
• Proven background in control path design.
• Direct experience with on-chip bus interfaces (PCIe, AXI, MDIO, I2C, SPI).
• Must be local to the Bay Area.

Responsabilidades

• Develop, simulate, and verify Verilog/SystemVerilog RTL code.
• Execute full FPGA development flow: synthesis, place&route, timing closure, and in-system debugging.
• Collaborate with hardware and software teams for rapid bring-up and debugging of next-gen platforms.
• Participate in RTL code reviews and PCB/schematic design reviews.

Conhecimentos

Verilog

SystemVerilog

RTL design

Control path design

Bus interfaces (PCIe etc)

Descrição da oferta de emprego

Arista Networks is seeking a Hardware Design Engineer to drive FPGA development for high-speed networking platforms in the Bay Area. You will own RTL/verification for the control path, collaborate with cross-functional hardware, software, and manufacturing teams, and push designs from concept through production.

The role emphasizes hands-on Verilog/SystemVerilog RTL coding, on-chip bus interfaces, and end-to-end FPGA flow, including timing closure and lab validation.