FPGA Design Engineer

Arista Networks, Inc.; California; On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical, Dental, Vision

Wellbeing programs

Bonuses and equity

Job summary

Arista Networks, Inc. is seeking a seasoned FPGA Design Engineer to join the Hardware Design Engineering team in California.

You will own the full design lifecycle for high-performance control path FPGAs powering Arista’s data center platforms, from requirements to verification and production support, collaborating with HW and SW teams. Role emphasizes RTL development in Verilog/SystemVerilog, FPGA flow, and system integration, with opportunities to work on PCIe, Ethernet, and AI-scale

Qualifications

• 5+ years of hands-on Verilog/SystemVerilog RTL design.
• Proven background in Control Path design.
• Direct experience with On-Chip Bus interfaces (e.g., PCIe, AXI, SPI, I2C, MDIO).
• Local to the Bay area.

Responsibilities

• RTL Development & Verification: Develop, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
• FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
• System-Level Integration: Collaborate with hardware and software teams to drive bring-up and debugging of next-generation network switch platforms.
• Design & Architecture Reviews: Participate in peer RTL code reviews and PCB schematic reviews.
• Toolchain Automation: Develop Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows.

Skills

Verilog/SystemVerilog RTL design

Control Path design

On-Chip bus interfaces (PCIe, AXI, etc

Python scripting

Tools

Python/Tcl/Shell scripting

Job description

Who You’ll Work With

You will work closely with cross-functional hardware, software, and manufacturing engineering teams to innovate new system architectures and drive FPGA development from initial concept to final delivery.

What You’ll Do

Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscaler data centers, and bleeding-edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments.

As a core member of the FPGA Design and Verification team, you will drive the development of high-performance control path FPGAs powering Arista’s flagship data center platforms. You will own the full design lifecycle—from gathering architectural requirements and reviewing board schematics to executing rigorous verification, leading system bring-up, and supporting production deployment.

Responsibilities

• RTL Development & Verification: Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
• FPGA Flow Implementation: Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
• System-Level Integration: Collaborate directly with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms.
• Design & Architecture Reviews: Actively participate in peer RTL code reviews, as well as PCB schematic and board design reviews.
• Toolchain Automation: Develop AI-skills, Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows.

Concepts & Skills You Will Gain

• Switching Architectures: Master data and control path architectures in modern Ethernet switches, alongside critical I/O interfaces (e.g., PCIe, Interlaken, Ethernet PHY/MAC, SMBus, SPI, MDIO, JTAG).
• Networking Protocols: Gain hands-on experience with Ethernet-based protocols, including PTP, sFlow, and PoE.
• Practical FPGA Engineering: Learn to navigate real-world design challenges, including tight timing closure, resource optimization, clock domain crossing, and complex state machine design.
• Multi-Vendor Ecosystems: Develop expertise across major vendor FPGA architectures, toolchains, and IDEs.
• Cross-Functional System Design: Build skills in interpreting complex PCB schematics, running advanced simulation frameworks, and solving multidisciplinary hardware/software challenges.

• 5 years or more of hands-on experience in Verilog/SystemVerilog RTL design.
• Proven background in Control Path design.
• Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI).
• Local to the Bay area.

Preferred

• Experience with Ethernet Data Path architecture and design.
• Hands-on experience with Streaming Bus interfaces (e.g., AXI-Stream).
• Background in FPGA resource management and timing closure.
• Proficiency in Python, Tcl, or general scripting for EDA tool automation.
• Lab Debugging & Validation: Utilize logic analyzers (LA), oscilloscopes, and vendor-specific debug tools for lab bring up, debug, and validation.

Compensation Information

The new hire base pay for this role has a pay range of $110,000 to $170,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The salary range provided reflects base pay only. As described above, this position may also be eligible for discretionary Arista bonuses and equity. US- based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.