FPGA/ASIC Design Engineer – Onsite (DoD Secret)

Innova Solutions Inc; Camden (NJ); On-site; USD 138,000 - 165,000; Full time

Job summary

Innova Solutions is seeking an FPGA/ASIC Design Engineer for a 12-month contract in Camden, NJ onsite. You will architect, implement, verify and validate complex FPGA/ASIC systems, targeting high-speed protocols and cryptographic blocks, using VHDL, Xilinx Vivado, and modern EDA flows.

Applicants should have 5+ years VHDL experience, strong Verilog/SystemVerilog, and C++ embedded SW; DoD Secret clearance preferred.

Qualifications

• Requires VHDL expertise with 5+ years experience.
• Proficiency in FPGA/ASIC design flow including verification and synthesis.
• Active DoD Secret Security Clearance preferred or ability to obtain.

Responsibilities

• Architect and implement FPGA/ASIC designs and validate via software integration tests.
• Develop end-to-end verification/test sequences using UVM and SystemVerilog assertions.
• Perform C++-based software validation on SOC evaluation boards running Linux.

Skills

VHDL

Vivado

C++ (OOP)

SystemVerilog Assertions

HLS

PCIe

Ethernet

Education

Bachelor's degree in Electrical Engineering or Computer Science

Master's degree in EE/CS preferred

Tools

Synopsys DC/Primetime/Synplify

Xilinx Vivado

Mentor Questa

Catapult (HLS)

Job description

Innova Solutions is seeking an FPGA/ASIC Design Engineer for a 12-month contract in Camden, NJ onsite. You will architect, implement, verify and validate complex FPGA/ASIC systems, targeting high-speed protocols and cryptographic blocks, using VHDL, Xilinx Vivado, and modern EDA flows.

Applicants should have 5+ years VHDL experience, strong Verilog/SystemVerilog, and C++ embedded SW; DoD Secret clearance preferred.