FPGA/ASIC Design Engineer

CHIPTON-ROSS Inc.; Camden (NJ); On-site; USD 90,000 - 120,000; Full time

Job summary

CHIPTON-ROSS Inc. is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, New Jersey. The ideal candidate will have over 3 years of experience implementing complex algorithms targeting ASICs and FPGAs, along with proficiency in VHDL and Xilinx FPGA/Vivado.

This role requires hands-on experience with architecture and verification, along with a Bachelor’s in Electrical Engineering or Computer Science. Candidates must also have US citizenship and an active secret clearance.

Qualifications

• 3+ years of experience with ASIC/FPGA algorithms.
• Experience with Ethernet protocol beyond IP instantiation is a plus.
• Hands-on with architecture, design, verification, and synthesis.

Responsibilities

• Architect and implement complex FPGA and/or ASIC systems.
• Write and debug tests/sequences for end-to-end simulation.
• Develop architectures for high-throughput designs with cryptographic algorithms.

Skills

VHDL

FPGA design/debug

Analytical/debug skills

Presentation skills

Mentoring EDA CDC/Lint/AC/RDC

Complex algorithm implementation

High-speed protocols knowledge

Education

Bachelor of Science in Electrical Engineering or Computer Science

Master of Science in Electrical Engineering or Computer Science

Tools

Xilinx FPGA/Vivado

UVM framework

SystemVerilog

C++

Job description

Chipton‑Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ.

Basic Qualifications (Required Skills/Experience)

• At least 3 years of experience implementing complex algorithms targeting ASIC/FPGAs.
• Proficiency in VHDL and FPGA design/debug with Xilinx FPGA/Vivado.
• Excellent analytical/debug skills.
• Good verbal, written, and presentation skills.
• US citizenship required; VHDL experience required for all candidates.
• Mid‑senior level – >5 years of VHDL experience; Xilinx FPGA design experience with Vivado.
• Hands‑on experience with multiple complex designs (architecture, design, verification, synthesis, STA).
• Experience with Ethernet protocol beyond IP instantiation is a plus.
• Experience mentoring EDA CDC/Lint/AC/RDC.

Position Responsibilities

• Architect, implement, verify, and validate complex FPGA and/or ASIC systems.
• Write and debug tests/sequences for end‑to‑end simulation on UVM framework, SystemVerilog assertions, and C++ SW‑driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
• Develop architectures for high‑throughput designs involving cryptographic algorithms with high‑speed protocols such as NVMe, PCIe/SRIOV, 10G‑400G Ethernet, TCP/IP, and IP development/integration targeting ARM SoC FPGAs (e.g., Xilinx MPSOC) and/or ASICs.

Preferred Qualifications (Desired Skills/Experience)

• High‑Level Synthesis (HLS) with Vivado.
• Embedded software C++ (OOP) and SystemVerilog assertions (SVA).
• Knowledge of high‑speed protocols (PCIe, TCP/IP, Ethernet).

Required Education

• Bachelor of Science in Electrical Engineering or Computer Science (or equivalent). Master of Science in Electrical Engineering or Computer Science preferred. Education must be accredited.

Work Hours

Full‑time, Monday–Friday 08:00 am–05:00 pm.

Additional

• Active secret clearance required.