Senior FPGA Engineer

Donatech Corporation; Cedar Rapids (IA); On-site; USD 110,000 - 160,000; Full time

Job summary

Donatech Corporation is seeking an FPGA design engineer to contribute to government programs in Cedar Rapids, IA. The role requires active Secret clearance and US citizenship.

You will design and verify FPGA solutions, integrate them on target hardware, and participate in Agile planning with cross-functional teams. The ideal candidate has 3+ years in FPGA/ASIC domains, strong VHDL/Verilog skills, and experience with toolchains like Vivado, Quartus, or Libero, plus familiarity with DDR/PCIe

Qualifications

• Requires STEM degree with 5+ years of experience or an advanced degree with 3+ years of experience.
• Active Final Secret Security Clearance required.
• Minimum 3 years of FPGA development/ASIC front end experience.
• Proficiency in VHDL/Verilog for FPGA/ASIC design.

Responsibilities

• Adhere to client engineering, development, and quality processes.
• Participate in Agile team meetings and planning activities.
• Design, verify and integrate FPGA solutions on target hardware.
• Support peer reviews and certification analyses; review FPGA artifacts.
• Manage changes and tasks using Jira.

Skills

VHDL/Verilog

FPGA development

SystemVerilog

Git

Subversion

C/C++

Unix scripting

Timing analysis

DDR/PCIe

Education

Bachelor's degree in STEM

Advanced degree (MS/PhD)

Tools

Vivado

Quartus

Libero

Job description

Position would require the candidate to be a W2 employee of Donatech.

US Citizenship Required.

Active Secret Clearance Required.

Responsibilities

• Adhere to all applicable Client Engineering Development and Quality processes, procedures, instructions and guidelines.
• Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan.
• Requirements, design and verification of FPGA solutions.
• Integration of developed FPGA on target hardware units.
• Supporting peer reviews and certification analysis activities.
• Peer reviewing FPGA development artifacts.
• Management of change request and task assignments through Jira.

Qualifications – Required

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
• An active U.S. government issued Final Secret Security Clearance is required.
• A minimum of 3 years professional experience in FPGA development, ASIC front end, or related areas.
• Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.
• Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
• Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).
• Strong debugging and troubleshooting skills for FPGA/ASIC systems.
• Proficiency with revision control concepts and tools (e.g., Git, Subversion).

Qualifications – Preferred

• Excellent communication and teamwork skills with the ability to work in a collaborative environment.
• Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet).
• Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog).
• Experience in ASIC / FPGA lab validation using advanced laboratory equipment.
• Experience with Unix, scripting, C/C++, and/or Perl.