CPU Architecture Verification Engineer

NUVACORE, Inc.; Austin, Northern (TX, KY); Hybrid; USD 130,000 - 210,000; Full time

Job summary

Nuvacore, Inc. in Austin, TX is seeking Verification Engineers at multiple levels to help prove architectural correctness of the Nuvacore CPU. You will join the design verification team and drive verification across the architecture and golden model.

You will build stimuli, checkers, and flows, collaborate with architecture and RTL, and support emulation, FPGA, and silicon bring-up across seniority levels.

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience on CPU or complex digital design.
• Strong knowledge of CPU architecture and micro-architecture with ISA knowledge (x86/ARM/RISC-V).
• Hands-on functional verification: test plans, testbenches, checkers, and coverage.
• Proficiency in C/C++/Rust and/or SystemVerilog, plus Python.
• Experience writing and debugging tests in assembly for CPU verification.

Responsibilities

• Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness.
• Environment Setup: Build and scale verification environments, co-simulation against a golden model.
• Test & Debug: Generate stimulus in assembly and RIS to exercise the ISA and corner cases.
• Coverage Closure: Define coverage, write monitors, and analyze results.
• Cross-functional Collaboration: Partner with architects and RTL to root-cause mismatches and support bring-up.

Skills

CPU architecture

Micro-architecture

C/C++/Rust

SystemVerilog

Python scripting

Education

Bachelor's or higher in Electrical/Computer Engineering, CS

Job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.

Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.

Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.

Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.

Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.

REQUIREMENTS — MUST TO HAVE

Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.

15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.

Strong knowledge of CPU architecture and micro-architecture — the instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).

Hands-on functional verification: test plans, testbenches, checkers, and coverage.

Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).

Experience writing and debugging tests in assembly for CPU verification.

REQUIREMENTS — NICE TO HAVE

Architectural / instruction-set verification against a golden reference model.

Random instruction sequence (RIS) stimulus generation.

Exceptions, interrupts, privilege levels, and virtualization.

Constrained-random verification and coverage-driven closure.

Assertions and formal verification.

Emulation/FPGA and silicon bring-up and debug (waveforms, trace).